Datasheet

267

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

21.13 Registers Description

21.13.1 USB General Registers

• Bits 7:1 – Reserved

These bits are reserved. Do not modify these bits.

• Bit 0 – UVREGE: USB pad regulator Enable

Set to enable the USB pad regulator. Clear to disable the USB pad regulator.

• Bit 7 – USBE: USB macro Enable Bit

Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the USB transceiver

and to disable the USB controller clock inputs.

• Bit 6 – Reserved

The value read from these bits is always 0. Do not set these bits.

• Bit 5 – FRZCLK: Freeze USB Clock Bit

Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power consumption.

Clear to enable the clock inputs.

• Bit 4 – OTGPADE: VBUS Pad Enable

Set to enable the VBUS pad. Clear to disable the VBUS pad.

Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the USB macro is

disable.

• Bits 3:1 – Reserved

The value read from these bits is always 0. Do not set these bits.

• Bit 0 – VBUSTE: VBUS Transition Interrupt Enable Bit

Set this bit to enable the VBUS Transition interrupt generation.

Clear this bit to disable the VBUS Transition interrupt generation.

Bit 7 6 5 4 321 0

- - - - - - - UVREGE UHWCON

Read/Write R/W R/W R R/W R R R R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 321 0

USBE - FRZCLK OTGPADE - - - VBUSTE USBCON

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Val-

0 0 1 0 000 0