Datasheet

223
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
19.7.4 USART MSPIM Control and Status Register n C - UCSRnC
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in the table. See “USART Control and Status
Register n C – UCSRnC” on page 211 for full description of the normal USART operation. The MSPIM is
enabled when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same
write operation where the MSPIM is enabled.
• Bit 5:3 - Reserved
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits
must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is
transmitted first. For details, see “Frame Formats” on page 192.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn.
For details, see “SPI Data Modes and Timing” on page 214.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings
determine the timing of the data transfer. For details, see “SPI Data Modes and Timing” on page 214.
19.7.5 USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation.
See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 213.
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn UCSRnC
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 19-3. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)