Datasheet

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

• Bits 7..6 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when

writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new

value) or to split the Erase and Write operations in two different operations. The Programming times for the

different modes are shown in the table below. While EEPE is set, any write to EEPMn will be ignored. During

reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero

disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is

set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is

zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the

bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are

correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must

be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The

following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that

the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the

software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by

the CPU, step 2 can be omitted. See “Memory Programming” on page 353 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write

Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the

Table 5-2. EEPROM Mode Bits

EEPM1 EEPM0 Programming Time Operation

0 0 3.4ms Erase and Write in one operation (Atomic Operation)

0 1 1.8ms Erase Only

1 0 1.8ms Write Only

1 1 – Reserved for future use