Datasheet

205
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
18.9 Hardware Flow Control
The hardware flow control can be enabled by software.
CTS
: (Clear to Send)
RTS
: (Request to Send)
18.9.1 Receiver Flow Control
The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control is to inform the
external transmitter when the internal receive Fifo is full. Thus the transmitter can stop sending characters. RTS
usage and so associated flow control is enabled using RTSEN bit in UCSRnD. Figure 18-8. shows a reception
example.
Figure 18-8. Reception Flow Control Waveform Example
Figure 18-9. RTS behavior
RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.
To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and stored in the
Receive Shift Register.
18.9.2 Transmission Flow Control
The transmission flow can be controlled by hardware using the CTS pin controlled by the external receiver. The
aim of the flow control is to stop transmission when the receiver is full of data (CTS
= 1). CTS usage and so
associated flow control is enabled using CTSEN bit in UCSRnD. The CTS
pin is sampled at each CPU write and
at the middle of the last stop bit that is currently being sent.
TXD
RTS
TXD
RXD
HOST
RXD
CTS
CTS
RTS
ATmega16U4/ATm
RTS
RXD
C1 C2
0 1 2
FIFO
1
CPU Read
Index
C3
10
RTS
RXD
Start Byte0
Stop
Start Byte1
Stop
Read from CPU
Start Byte2
1 additional byte may be sent
if the transmitter misses the RTS trig