Datasheet
20
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 5-2. Data Memory Map
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The device contains 512Bytes/1K bytes of data EEPROM memory. It is organized as a separate data space, in
which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM
Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 367,
page 371, and page 356 respectively.
32
R
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64
I/O
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$0000
-
$001
F
$0020
-
$005
F
$
FFFF
$0060
-
$00
FF
D
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160
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xt
I/O
R
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.
ISRAM end : $05FF / $0AFF
ISRAM start : $0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction