Datasheet

192
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data
output (TxDn) is changed.
Figure 18-3. Synchronous Mode XCKn Timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data
change. As the above figure shows, when UCPOLn is zero the data will be changed at rising XCKn edge and
sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at
rising XCKn edge.
18.3 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and
optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame
formats:
 1 start bit
 5, 6, 7, 8, or 9 data bits
 no, even or odd parity bit
 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. The following figure illustrates the possible combinations
of the frame formats. Bits inside brackets are optional.
Figure 18-4. Frame Formats
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
St Start bit, always low
(n) Data bits (0 to 8)
P Parity bit. Can be odd or even
Sp Stop bit, always high
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME