Datasheet

183
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master
clock generator. When the SS
pin is driven high, the SPI slave will immediately reset the send and receive logic,
and drop any partially received data in the Shift Register.
17.1.2 Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS
pin.
If SS
is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically,
the pin will be driving the SS
pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven
low by peripheral circuitry when the SPI is configured as a Master with the SS
pin defined as an input, the SPI
system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid
bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becom-
ing a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt
routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS
is
driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by
a slave select, it must be set by the user to re-enable SPI Master mode.
17.1.3 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by
control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 17-3 and Figure 17-4 on page
184. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for
data signals to stabilize. This is clearly seen by summarizing Table 17-3 and Table 17-4 on page 185, as done
below:
Table 17-2. CPOL and CPHA Functionality
Leading Edge Trailing eDge SPI Mode
CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0
CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1
CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2
CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3