Datasheet

180
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI,
line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will
synchronize the Slave by pulling high the Slave Select, SS
, line.
When configured as a Master, the SPI interface has no automatic control of the SS
line. This must be handled
by user software before communication can start. When this is done, writing a byte to the SPI Data Register
starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the
SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in
the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it
into SPDR, or signal the end of packet by pulling high the Slave Select, SS
line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS
pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS
pin is driven low. As one byte has been
completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR
before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 17-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direction. This means
that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
When receiving data, however, a received character must be read from the SPI Data Register before the next
character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling
of the clock signal, the frequency of the SPI clock should never exceed f
osc
/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS
pins is overridden according to
the table below. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 72.
Note: 1. See “Alternate Functions of Port B” on page 74 for a detailed description of how to define the direction of the
user defined SPI pins.
Table 17-1. SPI Pin Overrides
(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
MISO Input User Defined
SCK User Defined Input
SS User Defined Input
SHIFT
ENABLE