Datasheet

179

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

17. Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega16U4/ATmega32U4 and peripheral devices or between several AVR devices.

The SPI includes the following features:

•

Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 214.

The Power Reduction SPI bit, PRSPI, in “Power Reduction Register 0 - PRR0” on page 47 must be written to

zero to enable SPI module.

Figure 17-1. SPI Block Diagram

(1)

Note: 1. Refer to “Pinout” on page 3, and Table 10-3 on page 74 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2 on page 180. The

system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS

pin of the desired Slave. Master and Slave prepare

the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the

SPI2X

DIVIDER

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