Datasheet

174
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter4, and a compare match will clear TCNT4. This register has the same function in Normal mode
and PWM modes.
Note that, if a smaller value than three is written to the Output Compare Register C, the value is automatically
replaced by three as it is a minimum value allowed to be written to this register.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit
Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section “Accessing
10-bit Registers” on page 160.
15.12.11OCR4D – Timer/Counter4 Output Compare Register D
The output compare register D is an 8-bit read/write register.
The Timer/Counter Output Compare Register D contains data to be continuously compared with
Timer/Counter4. Actions on compare matches are specified in TCCR4A. A compare match does only occur if
Timer/Counter4 counts to the OCR4D value. A software write that sets TCNT4 and OCR4D to the same value
does not generate a compare match.
A compare match will set the compare interrupt flag OCF4D after a synchronization delay following the compare
event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit
Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section “Accessing
10-bit Registers” on page 160.
15.12.12TIMSK4 – Timer/Counter4 Interrupt Mask Register
• Bit 7- OCIE4D: Timer/Counter4 Output Compare Interrupt Enable
When the OCIE4D bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Compare
Match D interrupt is enabled. The corresponding interrupt at vector $010 is executed if a compare match D
occurs. The Compare Flag in Timer/Counter4 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 6 - OCIE4A: Timer/Counter4 Output Compare Interrupt Enable
When the OCIE4A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Compare
Match A interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare match A
occurs. The Compare Flag in Timer/Counter4 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 - OCIE4B: Timer/Counter4 Output Compare Interrupt Enable
When the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Compare
Match B interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare match B
occurs. The Compare Flag in Timer/Counter4 is set (one) in the Timer/Counter Interrupt Flag Register.
Bit 76543210
MSB LSB OCR4D
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
OCIE4D OCIE4A OCIE4B TOIE4 TIMSK4
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000