Datasheet

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

15.10.1 Fault Protection Trigger Source

The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alternatively the Analog

Comparator output can be used as trigger source for the Fault Protection unit. The Analog Comparator is

selected as trigger source by setting the

Fault Protection Analog Comparator (FPAC4) bit in the Timer/Counter4

Control Register

(TCCR4D). Be aware that changing trigger source can trigger a Fault Protection mode.

Therefore it is recommended to clear the FPF4 flag after changing trigger source, setting edge detector or

enabling the Fault Protection.

Both the external interrupt pin (INT0) and the

Analog Comparator output (ACO) inputs are sampled using the

same technique as for the T0 pin (Figure 12-1 on page 92). The edge detector is also identical. However, when

the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by

four system clock cycles. An Input Capture can also be triggered by software by controlling the port of the INT0

pin.

15.10.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input

is monitored over four samples, and all four must be equal for changing the output that in turn is used by the

edge detector.

The noise canceler is enabled by setting the

Fault Protection Noise Canceler (FPNC4) bit in Timer/Counter4

Control Register D (TCCR4D). When enabled the noise canceler introduces additional four system clock cycles

of delay from a change applied to the input. The noise canceler uses the system clock and is therefore not

affected by the prescaler.

15.11 Accessing 10-bit Registers

If 10-bit values are written to the TCNTn and OCRnA/B/C/D registers, the 10-bit registers can be byte accessed

by the AVR CPU via the 8-bit data bus using two read or write operations. The 10-bit registers have a common

2-bit Timer/Counter4 High Byte Register (TC4H) that is used for temporary storing of the two MSBs of the 10-bit

access. The same TC4H register is shared between all 10-bit registers. Accessing the low byte triggers the 10-

bit read or write operation. When the low byte of a 10-bit register is written by the CPU, the high byte stored in

the TC4H register, and the low byte written are both copied into the 10-bit register in the same clock cycle.

When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is copied into the

TC4H register in the same clock cycle as the low byte is read.

To do a 10-bit write, the high byte must be written to the TC4H register before the low byte is written. For a 10-

bit read, the low byte must be read before the high byte.