Datasheet

159
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 15-18. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clkT4
/8)
Figure 15-19. Timer/Counter Timing Diagram, with Prescaler (f
clkT4
/8)
15.10 Fault Protection Unit
The Timer/Counter4 incorporates a Fault Protection unit that can disable the PWM output pins, if an external
event is triggered. The external signal indicating an event can be applied via the external interrupt INT0 pin or
alternatively, via the analog-comparator unit. The Fault Protection unit is illustrated by the block diagram shown
in Figure 15-20. The elements of the block diagram that are not directly a part of the Fault Protection unit are
gray shaded.
Figure 15-20. Fault Protection Unit Block Diagram
When the Fault Protection mode is enabled by the Fault Protection Enable (FPEN4) bit and a change of the
logic level (an event) occurs on the
external interrupt pin (INT0), alternatively on the Analog Comparator output
(ACO), and this change confirms to the setting of the edge detector, a Fault Protection mode will be triggered.
When a Fault Protection is triggered, the COM4x bits are cleared, Output Comparators are disconnected from
the PWM output pins and the PORTB register bits are connected on the PWM output pins. The
Fault Protection
Enable
(FPEN4) is automatically cleared at the same system clock as the COM4nx bits are cleared. If the Fault
Protection Interrupt Enable
bit (FPIE4) is set, a Fault Protection interrupt is generated and the FPEN4 bit is
cleared. Alternatively the FPEN4 bit can be polled by software to figure out when the Timer/Counter has entered
to Fault Protection mode.
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
PCK
clk
Tn
(clk
PCK
/8)
TOVn
TCNTn
BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1
clk
PCK
clk
Tn
(clk
PCK
/8)
Analog
Comparator
Noise
Canceler
INT0
Edge
Detector
FPAC4 FPNC4 FPES4
ACO*
FPEN4
Timer/Counter4
FAULT_PROTECTION (Int. Req.)