Datasheet

156
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
15.8.4 PWM6 Mode
The PWM6 Mode (PWM4A = 1, WGM41 = 1, and WGM40 = x) provide PWM waveform generation option e.g.
for controlling Brushless DC (BLDC) motors. In the PWM6 Mode the OCR4A Register controls all six Output
Compare waveforms as the same Waveform Output (OCW4A) from the Waveform Generator is used for
generating all waveforms. The PWM6 Mode also provides an Output Compare Override Enable Register
(OC4OE) that can be used with an instant response for disabling or enabling the Output Compare pins. If the
Output Compare Override Enable bit is cleared, the actual value from the port register will be visible on the port
pin.
The PWM6 Mode provides two counter operation modes, a single-slope operation and a dual-slope operation. If
the single-slope operation is selected (the WGM40 bit is set to 0), the counter counts from BOTTOM to TOP
(defined as OCR4C) then restart from BOTTOM like in Fast PWM Mode. The PWM waveform is generated by
setting (or clearing) the Waveform Output (OCW4A) at the Compare Match between OCR4A and TCNT4, and
clearing (or setting) the Waveform Output at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM). The Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches the TOP and, if the
interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
Whereas, if the dual-slope operation is selected (the WGM40 bit is set to 1), the counter counts repeatedly from
BOTTOM to TOP (defined as OCR4C) and then from TOP to BOTTOM like in Phase and Frequency Correct
PWM Mode. The PWM waveform is generated by setting (or clearing) the Waveform Output (OCW4A) at the
Compare Match between OCR4A and TCNT4 when the counter increments, and clearing (or setting) the
Waveform Output at the he Compare Match between OCR4A and TCNT4 when the counter decrements. The
Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches the BOTTOM and, if the interrupt is
enabled, the interrupt handler routine can be used for updating the compare value.
The timing diagram for the PWM6 Mode in single-slope operation (WGM41 = 0) when the COM4A1:0 bits are
set to “10” is shown in Figure 15-15 on page 157. The counter is incremented until the counter value matches
the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT4 value is in the timing
diagram shown as a histogram for illustrating the single-slope operation. The timing diagram includes Output
Compare pins OC4A
and OC4A, and the corresponding Output Compare Override Enable bits
(OC4OE1..OC4OE0).