Datasheet

153
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
operation. The counter counts from BOTTOM to TOP (defined as OCR4C) then restarts from BOTTOM. In non-
inverting Compare Output mode the Waveform Output (OCW4x) is cleared on the Compare Match between
TCNT4 and OCR4x and set at BOTTOM. In inverting Compare Output mode, the Waveform Output is set on
Compare Match and cleared at BOTTOM. In complementary Compare Output mode the Waveform Output is
cleared on the Compare Match and set at BOTTOM.
Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the
Phase and Frequency Correct PWM mode that use dual-slope operation. This high frequency makes the fast
PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows
physically small sized external components (coils, capacitors), and therefore reduces total system cost.
The timing diagram for the fast PWM mode is shown in Figure 15-13. The counter is incremented until the
counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The
TCNT4 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The
diagram includes the Waveform Output in non-inverted and inverted Compare Output modes. The small
horizontal line marks on the TCNT4 slopes represent Compare Matches between OCR4x and TCNT4.
Figure 15-13. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches TOP. If the interrupt is enabled,
the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit
allows generation of PWM waveforms on the OC4x pins. Setting the COM4x1:0 bits to two will produce a non-
inverted PWM and setting the COM4x1:0 to three will produce an inverted PWM output. Setting the COM4x1:0
bits to one will enable complementary Compare Output mode and produce both the non-inverted (OC4x) and
inverted output (OC4x
). The actual value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by setting (or clearing) the Waveform Output (OCW4x) at the
Compare Match between OCR4x and TCNT4, and clearing (or setting) the Waveform Output at the timer clock
cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The
N variable represents the number of steps in single-slope operation. The value of N equals either to the
TOP value.
The extreme values for the OCR4C Register represents special cases when generating a PWM waveform
output in the fast PWM mode. If the OCR4C is set equal to BOTTOM, the output will be a narrow spike for each
MAX+1 timer clock cycle. Setting the OCR4C equal to MAX will result in a constantly high or low output
(depending on the polarity of the output set by the COM4x1:0 bits.)
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCWnx
OCWnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
f
OCnxPWM
f
clkT4
N
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