Datasheet

150
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
15.6.2 Enhanced Compare/PWM mode
When the bit ENHC4 of TCCR4E register is set, the Enhanced Compare/PWM mode is enabled. This mode
allows user to add an accuracy bit to Output Compare Register OCR4A, OCR4B, and OCR4D. Like explained
previously, a compare condition appears when one of the three Output Compare Registers (OCR4A/B/D)
matches the value of TCNT4 (10-bits resolution). In basic PWM Mode, the corresponding enabled output
toggles on the Compare Match. The Enhanced Compare/PWM mode introduces a bit that determines on which
internal clock edge the Compare Match condition is actually signalled. That means that the corresponding
outputs will toggle on the standard clock edge (like in Normal mode) if the LSB of OCR4A/B/D is ‘0’, or on the
opposite (next) edge if the LSB is ‘1’.
User will notice that between Normal and Enhanced PWM modes, the output frequency will be identical, while
the PWM resolution will be better in second case.
Writing to the Output Compare registers OCR4A/B/D or reading them will be identical in both modes. In
Enhanced mode, user must just consider that the TC4H register can be up to 3-bits wide (and have the same
behavior than during 2-bits operation). That will concern OCR4A, OCR4B and OCR4D registers accesses only.
Indeed, the OCR4C register must not include the additional accuracy bit, and remains in the resolution that
determines the output signal period.
Figure 15-10. How Register Access Works in Enhanced Mode
Figure 15-10 shows that the true OCR4A/B/D value corresponds to the value loaded by the user shifted on the
right in order to transfer the least significant bit directly to the Waveform generation module.
The maximum available resolution is 11-bits, but any other resolution can be specified. For example, a 8-bits
resolution will allow to obtain the same frequency than a Normal PWM mode with 7-bits resolution.
Example:
 PLL Postcaler output = 64MHz, No Prescaler on Timer/Counter4.
 Setting OCR4C = 0x7F determines a full 7-bits theoretical resolution, and so a 500kHz output
frequency.
 Setting OCR4A = 0x85 (= b’10000101’) signifies that the true value of “Compare A” register is 0x42
(b’01000010’) and that the Enhanced bit is set. That means that the duty cycle obtained (51.95%)
will be the intermediate value between duty cycles that can be obtained by 0x42 and 0x43 Compare
values (51.56%, 52.34%).
9 6 3 15
7
420
8
10
9 6 3 15
7
420
8
(TC4H) (OCR4A/B/D)
Output Compare Module A/B/D
Waveform Generation
Enhanced
Mode
Pin Toggle
True
OCR4A/B/D
User Interface Side
Timer Logic Side
ENHC4
TCNT4<9:0>
OCR4C<9:0>
Configuration
bits
(LSB)