Datasheet

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Figure 4-6. Single Cycle ALU Operation

4.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each

have a separate program vector in the program memory space. All interrupts are assigned individual enable bits

which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to

enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when

Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section

“Memory Programming” on page 353 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.

The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the

different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and

next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot

Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63

for more information. The Reset Vector can also be moved to the start of the Boot Flash section by

programming the BOOTRST Fuse, see “Memory Programming” on page 353.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user

software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the

current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is

executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For

these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt

handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by

writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the

corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is

enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global

Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global

Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not

necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the

interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more

instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when

returning from an interrupt routine. This must be handled by software.

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU