Datasheet

142
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
compare match interrupts. The OCR4C holds the Timer/Counter TOP value, i.e. the clear on compare match
value. The Timer/Counter4 High Byte Register (TC4H) is a 2-bit register that is used as a common temporary
buffer to access the MSB bits of the Timer/Counter4 registers, if the 10-bit accuracy is used.
Interrupt request (overflow TOV4, compare matches OCF4A, OCF4B, OCF4D and fault protection FPF4)
signals are visible in the Timer Interrupt Flag Register (TIFR4) and Timer/Counter4 Control Register D
(TCCR4D). The interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK4) and the
FPIE4 bit in the Timer/Counter4 Control Register D (TCCR4D).
Control signals are found in the Timer/Counter Control Registers TCCR4A, TCCR4B, TCCR4C, TCCR4D, and
TCCR4E.
15.2.4 Synchronization
In asynchronous clocking mode the Timer/Counter4 and the prescaler allow running the CPU from any clock
source while the prescaler is operating on the fast peripheral clock (PCK) having frequency up to 64MHz. This is
possible because there is a synchronization boundary between the CPU clock domain and the fast peripheral
clock domain. Figure 15-2 on page 143 shows Timer/Counter 4 synchronization register block diagram and
describes synchronization delays in between registers. Note that all clock gating details are not shown in the
figure.
The Timer/Counter4 register values go through the internal synchronization registers, which cause the input
synchronization delay, before affecting the counter operation. The registers TCCR4A, TCCR4B, TCCR4C,
TCCR4D, OCR4A, OCR4B, OCR4C, and OCR4D can be read back right after writing the register. The read
back values are delayed for the Timer/Counter4 (TCNT4) register, Timer/Counter4 High Byte Register (TC4H)
and flags (OCF4A, OCF4B, OCF4D, and TOV4), because of the input and output synchronization.
The system clock frequency must be lower than half of the PCK frequency, because the synchronization
mechanism of the asynchronous Timer/Counter4 needs at least two edges of the PCK when the system clock is
high. If the frequency of the system clock is too high, it is a risk that data or control values are lost.