Datasheet

14
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4.
Note that LPM is not affected by the RAMPZ setting.
Figure 4-4. The Z-pointer used by ELPM and SPM
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as
zero. For compatibility with future devices, be sure to write these bits to zero.
4.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by
the CPU clock clk
CPU
, directly generated from the selected clock source for the chip. No internal clock division is
used.
Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz
with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Bit 7654321 0
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RAMPZ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000000 0
Bit (Individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU