Datasheet

133
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
14.10.3 Timer/Counter1 Control Register B – TCCR1B
14.10.4 Timer/Counter3 Control Register B – TCCR3B
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the
input from the Input Capture Pin (ICPn) is filtered. The filter function requires four successive equal valued
samples of the ICPn pin for changing its output. The input capture is therefore delayed by four Oscillator cycles
when the noise canceler is enabled.
Table 14-4. Waveform Generation Mode Bit Description
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0) Timer/Counter Mode of Operation TOP
Update of
OCRnx at
TOVn
Flag Set
on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP
8 1 0 0 0 PWM, Phase and Frequency Correct ICRn BOTTOM BOTTOM
9 1 0 0 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICRn TOP TOP
15 1 1 1 1 Fast PWM OCRnA TOP TOP
Bit 76543210
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0