Datasheet

131
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
14.10 16-bit Timer/Counter Register Description
14.10.1 Timer/Counter1 Control Register A – TCCR1A
14.10.2 Timer/Counter3 Control Register A – TCCR3A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC
respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the
normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one,
the OCnB output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is
connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the
WGMn3:0 bits setting. The table shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a
normal or a CTC mode (non-PWM).
Bit 76543210
COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1
A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 14-1. Compare Output Mode, non-PWM
COMnA1/COMnB1/COMnC1 COMnA0/COMnB0/COMnC0 Description
0 0
Normal port operation, OCnA/OCnB/OCnC
disconnected
0 1 Toggle OCnA/OCnB/OCnC on compare match
1 0
Clear OCnA/OCnB/OCnC on compare match (set
output to low level)
1 1
Set OCnA/OCnB/OCnC on compare match (set output
to high level)