Datasheet

120
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 14-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names
indicates the device number (n = n
for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C). The
elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
Figure 14-4. Output Compare Unit, Block Diagram
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
For the Normal and
Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The
double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the
counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses,
thereby making the output glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the
OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation
(the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore
OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low
byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP
Register since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first.
When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written.
Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-
bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 113.
14.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one
to the
Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear
the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings
define whether the OCnx pin is set, cleared or toggled).
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM