Datasheet

117
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
Count: Increment or decrement TCNTn by 1.
Direction: Select between increment and decrement.
Clear: Clear TCNTn (set all bits to zero).
clk
T
n
: Timer/Counter clock.
TOP: Signalize that TCNTn has reached maximum value.
BOTTOM: Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations:
Counter High (TCNTnH) containing the upper
eight bits of the counter, and
Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value
when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written.
This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the counter is
counting that will give unpredictable results. The special cases are described in the sections where they are of
importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each
timer
clock
(clk
T
n
). The clk
T
n
can be generated from an external or internal clock source, selected by the Clock Select
bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value
can be accessed by the CPU, independent of whether clk
T
n
is present or not. A CPU write overrides (has priority
over) all counter clear or count operations.
The counting sequence is determined by the setting of the
Waveform Generation mode bits (WGMn3:0) located
in the
Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx.
For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on
page 122.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0
bits. TOVn can be used for generating a CPU interrupt.
14.5 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-
stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied
via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps
can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the
time-stamps can be used for creating a log of the events.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn