Datasheet

112
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 14-1. 16-bit Timer/Counter Block Diagram
(1)
Note: 1. Refer to “Pinout” on page 3, Table 10-3 on page 74, and Table 10-6 on page 77 for Timer/Counter1 and 3 and
3 pin placement and description.
2. Tn only refers to T1 since T3 input is not available on the product
.
14.1.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are
all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures
are described in the section “Accessing 16-bit Registers” on page 113. The Timer/Counter Control Registers
(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as Int.Req.)
signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the
Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin.
The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or
decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock
select logic is referred to as the timer clock (clk
T
n
).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pin (OCnA/B/C). See “Output Compare Units” on page 119. The
compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an
Output Compare interrupt request.
ICFn (Int.Req.)
TOVn
(Int.Req.)
Clock Select
Timer/Counter
DATABUS
ICRn
=
=
=
TCNTn
Waveform
Generation
Waveform
Generation
Waveform
Generation
OCnA
OCnB
OCnC
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
TCCRnA TCCRnB TCCRnC
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
TCLK
OCRnC
OCRnB
OCRnA
(2)