ATmega16U4/ATmega32U4 8-bit Microcontroller with 16/32K bytes of ISP Flash and USB Controller DATASHEET Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16/32KB of In-System Self-Programmable Flash – 1.25/2.
• • • • • – Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – One 10-bit High-Speed Timer/Counter with PLL (64MHz) and Compare Mode – Four 8-bit PWM Channels – Four PWM Channels with Programmable Resolution from 2 to 16 Bits – Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits – Output Compare Modulator – 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain) – Programmable Serial USART with Hardware Flow Control
Pin Configurations (INT.6/AIN0) PE6 UVcc GND AREF PF0 (ADC0) PF1 (ADC1) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC 43 42 41 40 39 38 37 36 35 34 Pinout AVCC Figure 1-1. 44 1.
Block Diagram PF7 - PF4 VCC PC7 PC6 PF1 PF0 PORTF DRIVERS RESET Block Diagram XTAL2 Figure 2-1. XTAL1 2.1 PORTC DRIVERS GND DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTC DATA DIR. REG.
power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 78. 2.2.6 Port E (PE6,PE2) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated.
2.2.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Shorter pulses are not guaranteed to generate a reset. 2.2.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.2.16 XTAL2 Output from the inverting Oscillator amplifier. 2.2.
3. About 3.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the device is characterized. 3.2 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.
4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4-1.
operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0 Addr.
Figure 4-3. The X-, Y-, and Z-registers 15 7 R27 (0x1B) XH X-register 15 7 R29 (0x1D) YH Y-register Z-register 15 7 R31 (0x1F) ZH 0 0 7 R26 (0x1A) 0 7 R28 (0x1C) XL 0 0 YL 0 0 ZL 7 R30 (0x1E) 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (See “Instruction Set Summary” on page 418 for detailed information). 4.
4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ Bit Read/Write Initial Value 7 RAMPZ7 R/W 0 6 RAMPZ6 R/W 0 5 RAMPZ5 R/W 0 4 RAMPZ4 R/W 0 3 RAMPZ3 R/W 0 2 RAMPZ2 R/W 0 1 RAMPZ1 R/W 0 0 RAMPZ0 R/W 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting. Figure 4-4.
Figure 4-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.
5. AVR Memories This section describes the different memories in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 5-1. Memory Mapping Memory Mnemonic Size Start Address Flash End Address 32 Registers I/O Registers Ext I/O Registers Internal SRAM Notes: 5.1 1. 2.
Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14. Figure 5-1. Program Memory Map Program Memory 0x00000 Application Flash Section Boot Flash Section 0x7FFF (32KBytes) 5.
Figure 5-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 160 E xt I/O Reg. $0000 - $001F $0020 - $005F $0060 - $00FF ISRAM start : $0100 Internal S RAM ISRAM end : $05FF / $0AFF $FFFF 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3. Figure 5-3.
5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 5-3 on page 23. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down.
• Bits 7..6 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the table below.
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.
Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
Assembly Code Example(1) EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example(1) unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details.
6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 43. The clock systems are detailed below. Figure 6-1.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 PLL Prescaler Clock – clkPllPresc The PLL requires a 8MHz input. A prescaler allows user to use either a 8MHz or a 16MHz source (from a crystal or an external source), using a divider (by 2) if necessary.
6.2.1 Default Clock Source ATmega16U4 and ATmega32U4 The device is shipped with Low Power Crystal Oscillator (8.0 - 16MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock with an 8MHz crystal. See Table 28-5 on page 355 for an overview of the default Clock Selection Fuse setting. 6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC The device is shipped with Calibrated Internal RC oscillator (8.0MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the below table. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 6-2.
Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Crystal Oscillator, BOD enabled 16K CK 14CK 1 01 Crystal Oscillator, fast rising power 16K CK 14CK + 4.1ms 1 10 Crystal Oscillator, slowly rising power 16K CK 14CK + 65ms 1 11 Oscillator Source / Power Conditions Notes: 1. 2.
Table 6-6. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 1 11 Reserved Note: 6.5 1. These options should only be used if frequency stability at start-up is not important for the application. Calibrated Internal RC Oscillator The calibrated internal RC Oscillator by default provides a 8.0MHz clock. This frequency is nominal value at 3V and 25C.
register to change the oscillator frequency. The calibration range is ±40% and linear (calibration step ~0.4%). With typical process at 25°C the code should be 127 for 8MHz. Input value of 0x00 gives the lowest frequency, and 0xFF the highest. The temperature sensitivity is quite linear but as said previously depends on the process. To determine its slope, the frequency must be measured at two temperatures.
Table 6-9. Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK + 65ms 10 Power Conditions Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
Figure 6-5. Example of Clock Switching with Wake-up from Device upstream-resume 2 Upstream Resume from device USB non-Idle CPU Clock Idle Ext non-Idle (Suspend) RC 2 Ext External Oscillator RC oscillator 3ms 6.8 w atchdog wake-up from power-down Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
6.9 PLL The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface and/or High Speed Timer module, the PLL input is supplied from an external low-frequency clock (the crystal oscillator or external clock input pin from XTAL1). 6.9.1 Internal PLL The internal PLL in the device generates a clock frequency between 32MHz and 96MHz from nominally 8MHz input.
Select_external_clock(); Enable_pll(); Disable_RC_clock(); while (!Pll_ready()); Usb_unfreeze_clock(); // // // // // CLKSEL0.CLKS = 1; PLLCSR.PLLE = 1; CLKSEL0.RCE = 0; while (PLLCSR.PLOCK != 1); USBCON.
6.11 Register Description 6.11.1 CLKSEL0 – Clock Selection Register 0 Bit Read/Write Initial Value 7 RCSUT1 R/W 0 6 RCSUT0 R/W 0 5 EXSUT1 R/W 0 4 EXSUT0 R/W 0 3 2 RCE EXTE R/W R/W See Bit Description 1 R 0 CLKS R/W CLKSEL0 • Bit 7-6 – RCSUT[1:0]: SUT for RC oscillator These two bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits.
6.11.3 CLKSTA – Clock Status Register Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 1 RCON R 0 EXTON R CLKSTA • Bit 7-2 - Reserved bits These bits are reserved and will always read as zero. • Bit 1 – RCON: RC Oscillator On This bit is set by hardware to one if the RC Oscillator is running. This bit is set by hardware to zero if the RC Oscillator is stopped.
Table 6-10. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved 6.11.
• Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started. Note that the Calibrated 8MHz Internal RC oscillator is automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set. The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscillator and avoid extra-consumption. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock.
Figure 6-7. PLL Postcaler operation with division factor = 1.5 Fi 2 Fi x --3 • Bit 3:0 – PDIV3:0 PLL Lock Frequency These bits configure the PLL internal VCO clock reference according to the required output frequency value.
7. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 88 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped.
7.7 Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
7.8.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
7.9 Register Description 7.9.1 Sleep Mode Control Register – SMCR The Sleep Mode Control Register contains control bits for power management. Bit Read/Write Initial Value 7 – R 0 6 – R 0 5 – R 0 4 – R 0 3 SM2 R/W 0 2 SM1 R/W 0 1 SM0 R/W 0 0 SE R/W 0 SMCR • Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the six available sleep modes as shown in Table 7-2. Table 7-2.
• Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 - Res: Reserved bit This bit is reserved and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.
• Bit 0 - PRUSART1: Power Reduction USART1 Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 8-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF USBRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register USB Reset Detection Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 8-1 on page 53.
Figure 8-3. MCU Start-up, RESET Extended Externally VCC VPOR VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 8.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 29-3 on page 386) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Table 8-1. BODLEVEL Fuse Coding BODLEVEL 2..0 Fuses Min. VBOT 111 Table 8-2. Typ. VBOT Max. VBOT Units BOD Disabled 110 1.8 2.0 2.2 101 2.0 2.2 2.4 100 2.2 2.4 2.6 011 2.4 2.6 2.8 010 3.2 3.4 3.6 001 3.3 3.5 3.7 000 4.0 4.3 4.5 V BOD characteristics Symbol Parameter Min. VHYST Brown-out Detector Hysteresis tBOD Min Pulse Width on Brown-out Reset Typ. 50 Max.
Figure 8-6. Watchdog Reset During Operation CC CK 8.7 USB Reset When the USB controller is enabled and configured with the USB Reset CPU feature enabled and if a valid USB Reset signalling is detected on the bus, the CPU core is reset but the USB controller remains enabled and attached. This feature may be used to enhance device reliability. Figure 8-7. USB Reset During Operation (USB Lines) CC 8.
consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 8-3. Symbol Parameter Condition VCC=2.7 VBG Bandgap reference voltage tBG Bandgap reference start-up time IBG Bandgap reference current consumption TA=25°C Min. Typ. Max. Units 1.0 1.1 1.2 V 40 70 µs VCC=2.7 TA=25°C VCC=2.7 10 TA=25°C µA Watchdog Timer ATmega16U4/ATmega32U4 has an Enhanced Watchdog Timer (WDT).
case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively.
Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
8.10 Register Description 8.11 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value 7 – R 0 6 – R 0 5 USBRF R 0 4 3 JTRF WDRF R/W R/W See Bit Description 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR • Bit 7..6 - Reserved These bits are reserved and should be read as 0. Do not set these bits.
8.11.1 Watchdog Timer Control Register - WDTCSR Bit Read/Write Initial Value 7 WDIF R/W 0 6 WDIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in the following table. Table 8-5. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 62
9. Interrupts This chapter describes the specifics of the interrupt handling as performed in ATmega16U4/ATmega32U4. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 9.1 Interrupt Vectors in ATmega16U4/ATmega32U4 Table 9-1. Reset and Interrupt Vectors(cont’d) Vector No.
Table 9-1. Reset and Interrupt Vectors(cont’d) Vector No.
9.2 Register Description 9.2.1 MCU Control Register – MCUCR Bit Read/Write Initial Value 7 JTD R/W 0 6 – R 0 5 – R 0 4 PUD R/W 0 3 – R 0 2 – R 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
10. I/O-Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 1. PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 10-1 summarizes the control signals for the pin value Table 10-1.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 104. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4.
Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
10.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown below. Table 10-3. Port Pin Port B Pins Alternate Functions Alternate Functions PB7 OC0A/OC1C/PCINT7/RTS (Output Compare and PWM Output A for Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7 or UART flow control RTS signal) PB6 OC1B/PCINT6/OC.
• OC1A/PCINT5/OC.4B/ADC12, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT5, Pin Change Interrupt source 5: The PB7 pin can serve as an external interrupt source. OC.4B: Timer 4 Output Compare B.
PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source Table 10-4. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/PCINT7/OC0A/O C1C/RTS PB6/PCINT6/OC1B/ OC.4B/ADC13 PB5/PCINT5/OC1A/ OC.
10.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown below. Table 10-6. Port C Pins Alternate Functions Port Pin Alternate Function PC7 ICP3/CLKO/OC4A(Input Capture Timer 3 or CLK0 (Divided System Clock) or Output Compare and direct PWM output A for Timer 4) PC6 OC.3A/OC4A (Output Compare and PWM output A for Timer/Counter3 or Output Compare and complementary PWM output A for Timer 4) PC5 PC4 PC3 PC2 Not present on pin-out. PC1 PC0 • ICP3/CLKO/OC.
The following table shows the alternate functions of Port C to the overriding signals shown in Figure 10-5 on page 72. Table 10-7. Overriding Signals for Alternate Functions in PC7..PC6 Signal Name PC7/ICP3/CLKO/OC.4A PC6/OC.3A/OC.4A PUOE SRE • (XMM<1) SRE • (XMM<2)|OC3A enable PUOV 0 0 DDOE SRE • (XMM<1) SRE • (XMM<2) DDOV 1 1 PVOE SRE • (XMM<1) SRE • (XMM<2) PVOV A15 if (SRE.XMM<2) then A14 else OC3A DIEOE 0 0 DIEOV 0 0 DI ICP3 input – AIO – – 10.3.
• T1/OC.4D/ADC9 – Port D, Bit 6 T1, Timer/Counter1 counter source. OC.4D: Timer 4 Output Compare D. This pin can be used to generate a high-speed PWM signal from Timer 4 module, complementary to OC.4D (PD7) signal. The pin has to be configured as an output (DDD6 set “one”) to serve this function. ADC9: Analog to Digital Converter, Channel 9. • XCK1/CTS – Port D, Bit 5 XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared).
Table 10-9. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T0/OC4D/ADC10 PD6/T1/OC4D/ADC9 PD5/XCK1/CTS PD4/ICP1/ADC8 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 10-10. Overriding Signals for Alternate Functions in PD3..
10.3.4 Alternate Functions of Port E The Port E pins with alternate functions are shown below. Table 10-11. Port Pin Port E Pins Alternate Functions Alternate Function PE7 Not present on pin-out. PE6 INT6/AIN0 (External Interrupt 6 Input or Analog Comparator Positive Input) PE5 PE4 Not present on pin-out. PE3 PE2 PE1 PE0 HWB (Hardware bootloader activation) Not present on pin-out.
This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 10-13.
Table 10-14. Overriding Signals for Alternate Functions in PF7..PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 10-15.
10.4 Register Description for I/O-Ports 10.4.1 MCU Control Register – MCUCR Bit Read/Writ e Initial Value 7 JTD R/W 6 – R 5 – R 4 PUD R/W 3 – R 2 – R 1 IVSEL R/W 0 IVCE R/W 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 68 for more details about this feature. 10.4.
10.4.
10.4.14 Port F Data Register – PORTF Bit Read/Write Initial Value 7 PORTF7 R/W 0 6 PORTF6 R/W 0 5 PORTF5 R/W 0 4 PORTF4 R/W 0 3 R/W 0 2 R/W 0 1 PORTF1 R/W 0 0 PORTF0 R/W 0 4 DDF4 R/W 0 3 R/W 0 2 R/W 0 1 DDF1 R/W 0 0 DDF0 R/W 0 4 PINF4 R/W N/A 3 R/W N/A 2 R/W N/A 1 PINF1 R/W N/A 0 PINF0 R/W N/A PORTF 10.4.15 Port F Data Direction Register – DDRF Bit Read/Write Initial Value 7 DDF7 R/W 0 6 DDF6 R/W 0 5 DDF5 R/W 0 DDRF 10.4.
ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 87
11. External Interrupts The External Interrupts are triggered by the INT6, INT3:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT[6;3:0] or PCINT7..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..
11.1 Register Description 11.1.1 External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value 7 ISC31 R/W 0 6 ISC30 R/W 0 5 ISC21 R/W 0 4 ISC20 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 EICRA • Bits 7..
selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.
11.1.5 Pin Change Interrupt Control Register - PCICR Bit 7 6 Read/Write Initial Value R 0 R 0 5 – R 0 4 – R 0 3 – R 0 2 – R 0 1 – R 0 0 PCIE0 R/W 0 PCICR • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector.
12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, or 3. 12.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 12-2. Prescaler for Synchronous Timer/Counters clk I/O Clear PSR10 Tn Synchronization Tn Synchronization CSn0 CSn0 CSn1 CSn1 CSn2 CSn2 TIMER/COUNTERn CLOCK SOURCE clkTn Note: TIMER/COUNTERn CLOCK SOURCE clkTn T3 input is not available on the ATmega16U4/ATmega32U4 products. “Tn” only refers to either T0 or T1 inputs.
13. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 13.
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 96. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 13.1.
bottom: Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not.
counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 13.4.
Figure 13-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
13.6.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM.
The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.
setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin. The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 13-10.
13.8 8-bit Timer/Counter Register Description 13.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value 7 COM0A1 R/W 0 6 COM0A0 R/W 0 5 COM0B1 R/W 0 4 COM0B0 R/W 0 3 – R 0 2 – R 0 1 WGM01 R/W 0 0 WGM00 R/W 0 TCCR0A • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Table 13-3. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected WGM02 = 1: Toggle OC0A on Compare Match 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: 1. Description A special case occurs when OCR0A equals TOP and COM0A1 is set.
The table shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 13-6. COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: 1.
13.8.2 Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value 7 FOC0A W 0 6 FOC0B W 0 5 – R 0 4 – R 0 3 WGM02 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
• Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 13-8. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 13.8.6 Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value 7 – R 0 6 – R 0 5 – R 0 4 – R 0 3 – R 0 2 OCIE0B R/W 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0 • Bits 7..3, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero.
OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
14. 16-bit Timers/Counters (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • 14.1 True 16-bit Design (i.e.
Figure 14-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select TCLK (2) Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 1. 2.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 293.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “Code Examples” on page 8. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1.
Assembly Code Example(1) TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1.
Figure 14-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count: Increment or decrement TCNTn by 1. Direction: Select between increment and decrement. Clear: Clear TCNTn (set all bits to zero). clkTn: Timer/Counter clock. TOP: Signalize that TCNTn has reached maximum value.
The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of the block diagram that are not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 14-3.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 12-1 on page 92). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
Figure 14-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 14-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf.
14.6.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 14.6.
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions.
matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 14-6.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three. Refer to Table 14-1 on page 131, Table 14-2 on page 132, and Table 14-3 on page 132.
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. Figure 14-8.
compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 14.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures.
Figure 14-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value Figure 14-13 shows the same timing data, but with the prescaler enabled. Figure 14-13.
14.10 16-bit Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value 7 COM1A1 6 COM1A0 5 COM1B1 4 COM1B0 3 COM1C1 2 COM1C0 1 WGM11 0 WGM10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 2 COM3C0 R/W 0 1 WGM31 R/W 0 0 WGM30 R/W 0 TCCR1 A 14.10.
The table shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 14-2. Compare Output Mode, Fast PWM(1) COMnA1/COMnB1/COMnC0 COMnA0/COMnB0/COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected.
Table 14-4.
• Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn).
14.10.6 Timer/Counter3 Control Register C – TCCR3C Bit Read/Write Initial Value 7 FOC3A W 0 6 – R 0 5 – R 0 4 – R 0 3 – R 0 2 – R 0 1 – R 0 0 – R 0 TCCR3C • Bit 7 – FOCnA: Force Output Compare for Channel A The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.
14.10.9 Output Compare Register 1 A – OCR1AH and OCR1AL Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 3 OCR1A[15:8] OCR1A[7:0] R/W R/W 0 0 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0 2 1 0 14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 3 OCR1B[15:8] OCR1B[7:0] R/W R/W 0 0 OCR1BH OCR1BL R/W 0 R/W 0 R/W 0 2 1 0 14.10.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 113. 14.10.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 63.) is executed when the OCFnC Flag, located in TIFRn, is set.
• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
15. 10-bit High Speed Timer/Counter4 15.1 Features • • • • • • • • • • • 15.
Figure 15-1.
compare match interrupts. The OCR4C holds the Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter4 High Byte Register (TC4H) is a 2-bit register that is used as a common temporary buffer to access the MSB bits of the Timer/Counter4 registers, if the 10-bit accuracy is used.
Figure 15-2.
15.3 Counter Unit The main part of the Timer/Counter4 is the programmable bi-directional counter unit. Figure 15-3 shows a block diagram of the counter and its surroundings. Figure 15-3. Counter Unit Block Diagram DATA BUS TOV4 clkT4 Timer/Counter4 Count Enable ( From Prescaler ) count TCNT4 clear Control Logic direction PLLTM1:0 PCK CK bottom top Signal description (internal signals): count: TCNT4 increment or decrement enable. direction: Select between increment and decrement.
15.4 Output Compare Unit The comparator continuously compares TCNT4 with the Output Compare Registers (OCR4A, OCR4B, OCR4C, and OCR4D). Whenever TCNT4 equals to the Output Compare Register, the comparator signals a match. A match will set the Output Compare Flag (OCF4A, OCF4B, or OCF4D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
Figure 15-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value Output Compare Waveform OCWnx Synchronized WFnx Latch Compare Value changes Counter Value Compare Value Unsynchronized WFnx Latch Glitch Output Compare Wafeform OCWnx 15.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC4x) bit.
Dead Time Generator The Dead Time Generator is provided for the Timer/Counter4 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times (non-overlapping times) for the Timer/Counter4 complementary output pairs OC4x and OC4x when the PWM mode is enabled and the COM4x1:0 bits are set to “01”.
OC4x and OC4x can have different dead time periods as the tnon-overlap / rising edge is adjusted by the 4-bit DT4H value and the tnon-overlap / falling edge is adjusted by the 4-bit DT4L value. Figure 15-8. The Complementary Output Pair, COM4x1:0 = 1 OCWnx OCnx OCnx (COMnx = 1) t non-overlap / rising edge 15.6 t non-overlap / falling edge Compare Match Output Unit The Compare Output Mode (COM4x1:0) bits have two functions.
Figure 15-9.
15.6.2 Enhanced Compare/PWM mode When the bit ENHC4 of TCCR4E register is set, the Enhanced Compare/PWM mode is enabled. This mode allows user to add an accuracy bit to Output Compare Register OCR4A, OCR4B, and OCR4D. Like explained previously, a compare condition appears when one of the three Output Compare Registers (OCR4A/B/D) matches the value of TCNT4 (10-bits resolution). In basic PWM Mode, the corresponding enabled output toggles on the Compare Match.
15.7 Synchronous update To avoid unasynchronous and incoherent values in a cycle, if a synchronous update of one of several values is necessary, all values can be updated at the same time at the end of the PWM cycle by the Timer controller. The new set of values is calculated by software and the effective update can be initiated by software. Figure 15-11.
Figure 15-12. Normal Mode, Timing Diagram TOVn Interrupt Flag Set OCnx Interrupt Flag Set TCNTn OCWnx (COMnx=1) 1 Period 2 3 4 The Timer/Counter Overflow Flag (TOV4) is set in the same clock cycle as the TCNT4 becomes zero. The TOV4 Flag in this case behaves like a 11th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt, that automatically clears the TOV4 Flag, the timer resolution can be increased by software.
operation. The counter counts from BOTTOM to TOP (defined as OCR4C) then restarts from BOTTOM. In noninverting Compare Output mode the Waveform Output (OCW4x) is cleared on the Compare Match between TCNT4 and OCR4x and set at BOTTOM. In inverting Compare Output mode, the Waveform Output is set on Compare Match and cleared at BOTTOM. In complementary Compare Output mode the Waveform Output is cleared on the Compare Match and set at BOTTOM.
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting the Waveform Output (OCW4x) to toggle its logical level on each Compare Match (COM4x1:0 = 1). The waveform generated will have a maximum frequency of fOC4 = fclkT4/4 when OCR4C is set to three.
Figure 15-14. Phase and Frequency Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWM waveforms on the OC4x pins.
15.8.4 PWM6 Mode The PWM6 Mode (PWM4A = 1, WGM41 = 1, and WGM40 = x) provide PWM waveform generation option e.g. for controlling Brushless DC (BLDC) motors. In the PWM6 Mode the OCR4A Register controls all six Output Compare waveforms as the same Waveform Output (OCW4A) from the Waveform Generator is used for generating all waveforms. The PWM6 Mode also provides an Output Compare Override Enable Register (OC4OE) that can be used with an instant response for disabling or enabling the Output Compare pins.
Figure 15-15. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT4 OCW4A OC4OE0 OC4A Pin OC4OE1 OC4A Pin OC4OE2 OC4B Pin OC4OE3 OC4B Pin OC4OE4 OC4D Pin OC4OE5 OC4D Pin The general I/O port function is overridden by the Output Compare value (OC4x / OC4x) from the Dead Time Generator if either of the COM4x1:0 bits are set. The Output Compare pins can also be overridden by the Output Compare Override Enable bits OC4OE5..OC4OE0.
Table 15-4. 15.9 Output Compare Pin configurations in PWM6 Mode COM4A1 COM4A0 OC4A Pin (PC6) OC4A Pin (PC7) 0 0 Disconnected Disconnected 0 1 OC4A • OC4OE4 OC4A • OC4OE5 1 0 OC4A • OC4OE4 OC4A • OC4OE5 1 1 OC4A • OC4OE4 OC4A • OC4OE5 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT4) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set.
Figure 15-18. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT4/8) clkPCK clkTn (clkPCK /8) OCRnx - 1 TCNTn OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-19. Timer/Counter Timing Diagram, with Prescaler (fclkT4/8) clkPCK clkTn (clkPCK /8) TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1 TOVn 15.10 Fault Protection Unit The Timer/Counter4 incorporates a Fault Protection unit that can disable the PWM output pins, if an external event is triggered.
15.10.1 Fault Protection Trigger Source The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alternatively the Analog Comparator output can be used as trigger source for the Fault Protection unit. The Analog Comparator is selected as trigger source by setting the Fault Protection Analog Comparator (FPAC4) bit in the Timer/Counter4 Control Register (TCCR4D). Be aware that changing trigger source can trigger a Fault Protection mode.
The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC4H register. The same principle can be used directly for accessing the OCRnA/B/C/C/D registers. Assembly Code Example ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCnH,r17 out TCNTn,r16 ; Read TCNTn into r17:r16 in r16,TCNTn in r17,TCnH ... C Code Example unsigned int i; ...
The following code examples show how to do an atomic read of the TCNTn register contents. Reading any of the OCRnA/B/C/D registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNTn register contents. Writing any of the OCRnA/B/C/D registers can be done by using the same principle.
15.12 Register Description 15.12.1 TCCR4A – Timer/Counter4 Control Register A Bit Read/Write Initial value 7 6 5 4 3 2 1 0 COM4A1 COM4A0 COM4B1 COM4B0 FOC4A FOC4B PWM4A PWM4B R/W 0 R/W 0 R/W 0 R/W 0 W 0 W 0 R/W 0 R/W 0 TCCR4A • Bits 7, 6 - COM4A1, COM4A0: Comparator A Output Mode, Bits 1 and 0 These bits control the behavior of the Waveform Output (OCW4A) and the connection of the Output Compare pin (OC4A).
Table 15-7. COM1A1..0 Compare Output Mode, Phase and Frequency Correct PWM Mode OCW1A Behavior OC4A Pin OC4A Pin Disconnected Disconnected 00 Normal port operation. 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting.
of the I/O pin it is connected to. The complementary OC4B output is connected only in PWM modes when the COM4B1:0 bits are set to “01”. Note that the Data Direction Register (DDR) bit corresponding to the OC4B pin must be set in order to enable the output driver. The function of the COM4B1:0 bits depends on the PWM4B and WGM40 bit settings. The table shows the COM4B1:0 bit functionality when the PWM4B bit is set to Normal Mode (non-PWM). Table 15-10. COM4B1..
Writing a logical one to this bit forces a change in the Waveform Output (OCW4A) and the Output Compare pin (OC4A) according to the values already set in COM4A1 and COM4A0. If COM4A1 and COM4A0 written in the same cycle as FOC4A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM4A1 and COM4A0 takes place as if a compare match had occurred, but no interrupt is generated.
Table 15-13. Division factors of the Dead Time prescaler DTPS41 DTPS40 Prescaler divides the T/C4 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8x • Bits 3..0 - CS43, CS42, CS41, CS40: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter4. Table 15-14.
15.12.3 TCCR4C – Timer/Counter4 Control Register C Bit Read/Write Initial value 7 6 5 4 COM4A1S COM4A0S COM4B1S COMAB0S R/W R/W R/W R/W 0 0 0 0 3 COM4D1 R/W 0 2 COM4D0 R/W 0 1 FOC4D R/W 0 0 PWM4D R/W 0 TCCR4C • Bits 7,6 - COM4A1S, COM4A0S: Comparator A Output Mode, Bits 1 and 0 These bits are the shadow bits of the COM4A1 and COM4A0 bits that are described in the section “TCCR4A – Timer/Counter4 Control Register A” on page 164.
The table shows the COM4D1:0 bit functionality when the PWM4D and WGM40 bits are set to Phase and Frequency Correct PWM Mode Table 15-17. COM4D1..
• Bit 3 - FPAC4: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter4 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter4 Fault Protection interrupt.
• Bit 6- ENHC4: Enhanced Compare/PWM Mode When this bit is set, the Waveform Generation Module works in enhanced mode: the compare registers OCR4A/B/D can welcome one more accuracy bit, while the LSB determines on which clock edge the Compare condition is signalled and the output pin level is updated.
• Bits 1:0 - TC49, TC48: Two MSB bits of the 10-bit accesses If 10-bit accuracy is used, the Timer/Counter4 High Byte Register (TC4H) is used for temporary storing the MSB bits (TC49, TC48) of the 10-bit accesses. The same TC4H register is shared between all 10-bit registers within the Timer/Counter4. Note that special procedures must be followed when accessing the 10-bit TCNT4 register via the 8-bit AVR data bus. These procedures are described in section “Accessing 10-bit Registers” on page 160. 15.12.
The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter4, and a compare match will clear TCNT4. This register has the same function in Normal mode and PWM modes. Note that, if a smaller value than three is written to the Output Compare Register C, the value is automatically replaced by three as it is a minimum value allowed to be written to this register.
• Bit 2 - TOIE4: Timer/Counter4 Overflow Interrupt Enable When the TOIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter4 occurs. The Overflow Flag (Timer4) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR4. 15.12.
The dead time delay of all Timer/Counter4 channels are adjusted by the dead time value register, DT4. The register consists of two fields, DT4H3..0 and DT4L3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC4x and the rising edge of OC4x. • Bits 7:4- DT4H3:DT4H0: Dead Time Value for OC4x Output The dead time value for the OC1x output. The dead time delay is set as a number of the prescaled timer/counter clocks.
16. Output Compare Modulator (OCM1C0A) 16.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 92. Figure 16-1.
16.2.1 Timing Example Figure 16-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 16-3.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16U4/ATmega32U4 and peripheral devices or between several AVR devices.
SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 17.1.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
Figure 17-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Figure 17-4.
17.2 Register Description 17.2.1 SPI Control Register – SPCR Bit Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
Table 17-5. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SCK Frequency fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64 17.2.2 SPI Status Register – SPSR Bit Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 – R 0 4 – R 0 3 – R 0 2 – R 0 1 – R 0 0 SPI2X R/W 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set.
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
18. USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR 1. TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC See “Pinout” on page 3, Table 10-8 on page 78 and for USART pin placement.
Figure 18-2. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector DDR_XCK 0 UMSEL 1 xcko UCPOL txclk 1 1 0 rxclk Signal description: txclk Transmitter clock (Internal Signal) rxclk Receiver base clock (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation xcko Clock output to XCK pin (Internal Signal).
Table 18-1.
basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Figure 18-3. Synchronous Mode XCKn Timing UCPOL = 1 XCK RxD / TxD Sample XCK UCPOL = 0 RxD / TxD Sample The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As the above figure shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0, and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit.
frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most significant bits written to the UDRn are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16.
Assembly Code Example(1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled).
18.6.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer.
recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition.
18.7.3 Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 18-6 on page 208) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable.
18.9 Hardware Flow Control The hardware flow control can be enabled by software. CTS: (Clear to Send) RTS: (Request to Send) HOST ATmega16U4/ATm TXD TXD RXD RXD CTS CTS RTS RTS 18.9.1 Receiver Flow Control The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can stop sending characters.
Figure 18-10. CTS behavior Write from CPU TXD Start Byte0 sample Stop Start Byte1 sample Stop Start Byte2 sample CTS 18.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 18-4 on page 206 to Table 18-11 on page 212. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
Table 18-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 3.6864MHz Baud Rate [bps] U2Xn = 0 UBRR fosc = 4.0000MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR fosc = 7.3728MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR U2Xn = 1 Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.
Table 18-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate [bps] UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.
18.11 USART Register Description 18.11.1 USART I/O Data Register n– UDRn Bit Read/Write Initial Value 7 RXB[7:0] TXB[7:0] R/W 0 6 5 4 3 2 1 0 UDRn (Read) UDRn (Write) R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDRn Register location.
• Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
• Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 – TXENn: Transmitter Enable n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled.
Table 18-8. UPMn Bit Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 18-9.
18.11.5 USART Control and Status Register n D– UCSRnD Bit 7 6 5 – Read/Write Initial Value R 0 4 – R 0 3 – R 0 – R 0 2 – R 0 – R 0 1 CTSEN R/W 0 0 RTSEN R/W 0 UCSRnD • Bits 7:2 – Reserved bits These bits are reserved and will be read as ‘0’. Do not set these bits. • Bits 1 – CTSEN: UART CTS Signal Enable Set this bit by firmware to enable the transmission flow control signal (CTS). Transmission will be enabled only if CTS input = 0.
19. USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • • • • • • • • 19.
Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in the following table. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. Table 19-1.
Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a reset since UBRRn is reset to zero.
Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
19.5 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
19.6 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: Master mode timing diagram The UCPOLn bit functionality is identical to the SPI CPOL bit The UCPHAn bit functionality is identical to the SPI CPHA bit The UDORDn bit functionality is identical to the SPI DORD bit However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
19.7 USART MSPIM Register Description The following section describes the registers used for SPI operation using the USART. 19.7.1 USART MSPIM I/O Data Register - UDRn The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “USART I/O Data Register n– UDRn” on page 209. 19.7.
19.7.3 USART MSPIM Control and Status Register n B - UCSRnB Bit Read/Write Initial Value 7 RXCIEn R/W 0 6 TXCIEn R/W 0 5 UDRIE R/W 0 4 RXENn R/W 0 3 TXENn R/W 0 2 R 1 1 R 1 0 R 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set.
19.7.4 USART MSPIM Control and Status Register n C - UCSRnC Bit Read/Write Initial Value 7 UMSELn1 R/W 0 6 UMSELn0 R/W 0 5 R 0 4 R 0 3 R 0 2 UDORDn R/W 1 1 UCPHAn R/W 1 0 UCPOLn R/W 0 UCSRnC • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in the table. See “USART Control and Status Register n C – UCSRnC” on page 211 for full description of the normal USART operation. The MSPIM is enabled when both UMSELn bits are set to one.
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20. 2-wire Serial Interface 20.1 Features • • • • • • • • • • 20.
The Power Reduction TWI bit, PRTWI bit in “Power Reduction Register 0 - PRR0” on page 47 must be written to zero to enable the 2-wire Serial Interface. 20.2.2 Electrical Interconnection As depicted in Figure 20-1 on page 225, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface.
Figure 20-3. START, REPEATED START and STOP Conditions SDA SCL STOP START START REPEATED START STOP 20.3.3 Address Packet Format All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 20-5. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 SLA+R/W 7 STOP, REPEATED START or Next Data Byte Data Byte 20.3.5 Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition.
the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process.
Figure 20-8. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: A REPEATED START condition and a data bit A STOP condition and a data bit A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Overview of the TWI Module SCL Slew-rate Control SDA Spike Filter Slew-rate Control Spike Filter Bus Interface Unit START / STOP Control Spike Suppression Arbitration detection Address/Data Shift Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator Bit Rate Generator Prescaler Bit Rate Register (TWBR) Ack Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status control TWI Unit Figure 20-9. 20.5.
20.5.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software.
together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus. When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus.
5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR.
Assembly Code Example ldi r16, (1<
Assembly Code Example 5 6 7 C Example Comments in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR if ((TWSR & 0xF8) != MT_SLA_ACK) ldi r16, DATA out TWDR, r16 ldi r16, (1<
Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 20-12 on page 240 to Figure 20-18 on page 248, circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero.
Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR value TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 – 0 TWIE X When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38.
Table 20-1.
Figure 20-12.
Figure 20-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 – 0 TWIE X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
Table 20-2.
Figure 20-14.
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 – 0 TWIE X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 20-3.
Figure 20-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 – 0 TWIE X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 20-4.
20.7.5 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see the table below. Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
20.8 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. Figure 20-20.
Figure 20-21.
20.9 TWI Register Description 20.9.1 TWI Bit Rate Register – TWBR Bit Read/Write Initial Value 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR • Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator Unit” on page 231 for calculating bit rates. 20.9.
• Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
Table 20-6. TWI Prescaler Bits TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 231. The value of TWPS1..0 is used in the equation. 20.9.4 TWI Data Register – TWDR Bit Read/Write Initial Value 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 20.9.6 TWI (Slave) Address Mask Register – TWAMR Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R 0 TWAM[6:0] Read/Write Initial Value R/W 0 R/W 0 R/W 0 R/W 0 – TWAMR • Bits 7..1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask.
21. USB Controller 21.1 Features • • • • Supports full-speed and low-speed Device role Complies with USB Specification v2.0 Supports ping-pong mode (dual bank) 832 bytes of DPRAM: – 1 endpoint 64 bytes max. (default control endpoint) – 1 endpoints of 256 bytes max., (one or two banks) – 5 endpoints of 64 bytes max., (one or two banks) • Crystal-less operation for low-speed mode 21.
21.3 Typical Application Implementation Depending on the target application power supply, the ATmega16U4/ATmega32U4 requires different hardware typical implementations. Figure 21-2. Operating Modes versus Frequency and Power-supply Max Operating Frequency (MHz) VCC (V) 5.5 16 MHz 4.5 USB compliant, with internal regulator 3.6 8 MHz 3.4 USB compliant, without internal regulator 3.0 2.7 USB not operational 2 MHz VCC min 0 21.3.1 Bus Powered Device Figure 21-3.
Figure 21-4. Typical Bus Powered Application with 3V I/O External 3V Regulator UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM DRs=22 UVSS UVSS UGND UID UID XTAL1 XTAL2 GND GND 21.3.2 Self Powered Device Figure 21-5. Typical Self Powered Application with 3.4V to 5.5V I/O External 3.4V - 5.
Figure 21-6. Typical Self Powered Application with 3.0V to 3.6 I/O External 3.0V - 3.6V Power Supply UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM DRs=22 UVSS UID UGND UID XTAL1 21.4 XTAL2 GND GND Crystal-less Operation To reduce external components count and BOM cost, the USB module can be configured to operate in lowspeed mode with internal RC oscillator as input source clock for the PLL.
21.6 General Operating Modes 21.6.1 Introduction The USB controller is disabled and reset after an hardware reset generated by: ̶ Power on reset ̶ External reset ̶ Watchdog reset ̶ Brown out reset ̶ JTAG reset But another available and optional CPU reset source is: ̶ USB End Of Reset In this case, the USB controller is reset, but not disabled (so that the device remains attached). 21.6.2 Power-on and Reset The next diagram explains the USB controller main states on power-on: Figure 21-7.
Figure 21-8. USB Interrupt System USB General Interrupt USB General Interrupt Vector USB Device Interrupt USB Endpoint/Pipe Interrupt Vector Endpoint Interrupt The USB hardware module distinguishes between USB General events and USB Endpoint events that are relevant with data transfers relative to each endpoint. Figure 21-9. USB General Interrupt Vector Sources VBUSTI USBINT.0 UPRSMI UDINT.6 EORSMI UDINT.5 USB General Interrupt Vector VBUSTE USBCON.0 UPRSME UDIEN.6 EORSME UDIEN.5 WAKEUPI UDINT.
Figure 21-10. USB Endpoint Interrupt Vector Sources Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 RXSTPE UEIENX.3 EPINT UEINT.X USB Endpoint Interrupt Vector RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
USBCON, USBSTA, USBINT UDCON (detach, ..) UDINT UDIEN Moreover, when FRZCLK is set, only the following interrupts may be triggered: 21.8 WAKEUPI VBUSTI Speed Control The speed selection (Full Speed or Low Speed) depends on the D+/D- pull-up. The LSM bit in UDCON register allows to select an internal pull up on D- (Low Speed mode) or D+ (Full Speed mode) data lines. Figure 21-11. Device Mode Speed Selection UCAP DETACH USB Regulator UDCON.0 LSM RPU RPU UDCON.2 D+ D- 21.
Table 21-1. Allocation and Reorganization USB Memory Flow Free memory Free memory Free memory Free memory 5 5 5 5 4 4 Lost memory 3 EPEN=0 (ALLOC=1) 4 3 (bigger size) 2 2 2 2 1 1 1 1 0 0 0 0 Endpoints activation Endpoint Disable Free its memory (ALLOC=0) Endpoint Activatation 4 Conflict EPEN=1 ALLOC=1 First, Endpoint 0 to Endpoint 5 are configured, in the growing order. The memory of each is reserved in the DPRAM.
Figure 21-12. Pad Behaviour Idle mode USBE=0 | DETACH=1 | suspend USBE=1 & DETACH=0 & suspend Active mode The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up the USB pad.
The “Session_valid” signal is active high when the voltage on the UVBUS pad is higher or equal to 1.4V. If lower than 1.4V, the signal is not active The VBUS status bit is set when “Session_valid” signal is active (VBUS > 1.4V) The VBUSTI flag is set each time the VBUS state changes The USB peripheral cannot attach to the bus while VBUS bit is not set 21.
21.13 Registers Description 21.13.1 USB General Registers Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 UVREGE R/W 0 UHWCON • Bits 7:1 – Reserved These bits are reserved. Do not modify these bits. • Bit 0 – UVREGE: USB pad regulator Enable Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 ID R 1 0 VBUS R 0 USBSTA • Bits 7:2 - Reserved The value read from these bits is always 0. Do not set these bits. • Bit 1 - ID: ID status This bit is always read as “1”, it has been conserved for compatibility with AT90USB64/128 (in which it indicates the value of the OTG ID pin). • Bit 0 – VBUS: VBus Flag The value read from this bit indicates the state of the VBUS pin.
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22. USB Device Operating Modes 22.1 Introduction The USB device controller supports full speed and low speed data transfers.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as an answer to the CLEAR_FEATURE USB command. 22.4 USB Reset When an USB reset is detected on the USB line (SE0 state with a minimum duration of 2.
A clear of EPEN acts as an endpoint reset (see “Endpoint Reset” on page 270 for more details). It also performs the next operation: The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept) It resets the data toggle field The DPRAM memory associated to the endpoint is still reserved See “Memory Management” on page 263 for more details about the memory allocation/reorganization. 22.
Setting DETACH will disconnect the pull-up on the D+ or D- pad (depending on full or low speed mode selected). Then, clearing DETACH will connect the pull-up on the D+ or D- pad. Figure 22-3. Detach a Device in Full-speed UVREF UVREF D+ D+ D- D- EN=1 Detach, then Attach EN=1 22.10 Remote Wake-up The “Remote Wake-up” (or “upstream resume”) feature is the only operation allowed to be sent by the device on its own initiative.
If a STALL request is set for a Control Endpoint and if a SETUP request occurs, the SETUP request has to be ACK’ed and the STALLRQ request and STALLEDI sent flags are automatically reset (RXSETUPI set, TXIN cleared, STALLED cleared, TXINI cleared...). This management simplifies the enumeration process management. If a command is not supported or contains an error, the firmware set the STALL request flag and can return to the main task, waiting for the next SETUP request.
22.12.2 Control Read The next figure shows a control read transaction. The USB controller has to manage the simultaneous write requests from the CPU and the USB host: SETUP USB line DATA SETUP RXSTPI HW IN STATUS IN OUT NAK SW RXOUTI TXINI OUT HW SW HW SW SW Wr Enable HOST Wr Enable CPU A NAK handshake is always generated at the first status stage command. When the controller detect the status stage, all the data written by the CPU are erased, and clearing TXINI has no effects.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can write data to the bank, and cleared by hardware when the bank is full .
Table 22-1. Abort Flow Endpoint Abort Clear UEIENX. TXINE NBUSYBK =0 Yes Disable the TXINI interrupt. Abort is based on the fact that no banks are busy, meaning that nothing has to be sent. No Endpoint reset Yes KILLBK=1 Kill the last written bank. KILLBK=1 Wait for the end of the procedure. No Abort done 22.15 Isochronous Mode 22.15.1 Underflow An underflow can occur during IN stage if the host attempts to read a bank which is empty. In this situation, the UNDERFI interrupt is triggered.
Figure 22-4. USB Device Controller Interrupt System UPRSMI UDINT.6 EORSMI UDINT.5 UPRSME UDIEN.6 EORSME UDIEN.5 WAKEUPI UDINT.4 WAKEUPE UDIEN.4 EORSTI UDINT.3 SOFI UDINT.2 SUSPI UDINT.0 USB Device Interrupt EORSTE UDIEN.3 SOFE UDIEN.2 SUSPE UDIEN.0 There are two kind of interrupts: processing (i.e. their generation are part of the normal processing) and exception (errors).
Figure 22-5. USB Device Controller Endpoint Interrupt System Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 TXOUTE UEIENX.3 Endpoint Interrupt EPINT UEINT.X RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
22.18 Registers 22.18.1 USB Device General Registers Bit 7 6 5 4 3 2 1 0 - - - - RSTCPU LSM RMWKUP DETACH Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 1 UDCON • Bits 7:4 - Reserved The value read from these bits is always 0. Do not set these bits. • Bit 3 - RSTCPU - USB Reset CPU bit Set this bit to 1 by firmware in order to reset the CPU on the detection of a USB End of Reset signal (without disabling the USB controller and Attached state).
Bit 7 6 5 4 3 2 1 0 - UPRSMI EORSMI WAKEUPI EORSTI SOFI - SUSPI 0 0 0 0 0 0 0 0 UDINT Read/Write Initial Value • Bit 7 - Reserved The value read from this bits is always 0. Do not set this bit. • Bit 6 - UPRSMI - Upstream Resume Interrupt Flag Set by hardware when the USB controller is sending a resume signal called “Upstream Resume”. This triggers an USB interrupt if UPRSME is set. Shall be cleared by software (USB clocks must be enabled before).
Bit 7 6 5 4 3 2 1 0 - UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE 0 0 0 0 0 0 0 0 UDIEN Read/Write Initial Value • Bit 7 - Reserved The value read from this bits is always 0. Do not set this bit. • Bit 6 - UPRSME - Upstream Resume Interrupt Enable Bit Set to enable the UPRSMI interrupt. Clear to disable the UPRSMI interrupt. • Bit 5 - EORSME - End Of Resume Interrupt Enable Bit Set to enable the EORSMI interrupt. Clear to disable the EORSMI interrupt.
Bit 7 6 5 4 3 ADDEN 2 1 0 UADD6:0 UDADDR Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 - ADDEN - Address Enable Bit Set to activate the UADD (USB address). Cleared by hardware. Clearing by software has no effect. See “Address Setup” on page 272 for more details.
Bit 7 6 5 4 3 2 1 0 - - - FNCERR - - - - 0 0 0 0 Read/Wri te Initial Value UDMFN R 0 0 0 0 • Bits 7:5 - Reserved The value read from these bits is always 0. Do not set these bits. • Bit 4 - FNCERR -Frame Number CRC Error Flag Set by hardware when a corrupted Frame Number in start of frame packet is received. This bit and the SOFI interrupt are updated at the same time. • Bits 3:0 - Reserved The value read from these bits is always 0. Do not set these bits. 22.18.
Bit 7 6 5 4 3 2 1 0 - - STALLRQ STALLRQC RSTDT - - EPEN Read/Write R R W W W R R R/W Initial Value 0 0 0 0 0 0 0 0 UECONX • Bits 7:6 - Reserved The value read from these bits is always 0. Do not set these bits. • Bit 5 - STALLRQ - STALL Request Handshake Bit Set to request a STALL answer to the host for the next handshake. Cleared by hardware when a new SETUP is received. Clearing by software has no effect. See “STALL Request” on page 273 for more details.
• Bits 5:1 - Reserved The value read from these bits is always 0. Do not set these bits. • Bit 0 - EPDIR - Endpoint Direction Bit Set to configure an IN direction for bulk, interrupt or isochronous endpoints. Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.
• Bit 6 - OVERFI - Overflow Error Interrupt Flag Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled). See Section 22.15, page 278 for more details. Shall be cleared by software. Setting by software has no effect. • Bit 5 - UNDERFI - Flow Error Interrupt Flag Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled). See Section 22.15, page 278 for more details.
- 1 for IN endpoint - 0 for OUT endpoint Can not be set or cleared by software. • Bits 1:0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) Flag Set by hardware to indicate the number of the current bank: 00bBank0 01bBank1 1xbReserved Can not be set or cleared by software.
• Bit 3 - RXSTPI - Received SETUP Interrupt Flag Set by hardware to signal that the current bank contains a new valid SETUP packet. An interrupt (EPINTx) is triggered (if enabled). Shall be cleared by software to handshake the interrupt. Setting by software has no effect. This bit is inactive (cleared) if the endpoint is an IN endpoint. • Bit 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag Set by hardware to signal that the current bank contains a new packet.
• Bit 3 - RXSTPE - Received SETUP Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent. Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent. • Bit 2 - RXOUTE - Received OUT Data Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent. Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent. • Bit 1 - STALLEDE - Stalled Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.
Bit 7 6 5 4 3 2 1 0 - EPINT D6 EPINT D5 EPINT D4 EPINT D3 EPINT D2 EPINT D1 EPINT D0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 UEINT • Bit 7 - Reserved The value read from these bits is always 0. Do not set these bits. • Bits 6:0 - EPINT6:0 - Endpoint Interrupts Bits Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding endpoint interrupt enable bit is set. Cleared by hardware when the interrupt source is served.
23. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN+ and negative pin AIN-. When the voltage on the positive pin AIN+ is higher than the voltage on the negative pin AIN-, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
23.1 Register Description 23.1.1 ADC Control and Status Register B – ADCSRB Bit Read/Write Initial Value 7 ADHSM R 0 6 ACME R/W 0 5 MUX5 R/W 0 4 – R 0 3 ADTS3 R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer is connected to the negative input to the Analog Comparator.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists.
23.2.1 Digital Input Disable Register 1 – DIDR1 Bit Read/Write Initial Value 7 – R 0 6 – R 0 5 – R 0 4 – R 0 3 – R 0 2 – R 0 1 – R 0 0 AIN0D R/W 0 DIDR1 • Bit 0 – AIN0D: AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
24. Analog to Digital Converter - ADC 24.1 Features • • • • • • • • • • • • • • • 10/8-bit Resolution 0.5LSB Integral Non-linearity ±2LSB Absolute Accuracy 65 - 260µs Conversion Time Up to 15kSPS at Maximum Resolution Twelve Multiplexed Single-Ended Input Channels One Differential amplifier providing gain of 1x - 10x - 40x - 200x Temperature sensor Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
Figure 24-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[3:0] TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC MUX0 MUX2 15 ADC CTRL.
24.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
Figure 24-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously.
Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Figure 24-7.
then to “1”), only extended conversions are performed. The result from the extended conversions will be valid. See “Prescaling and Conversion Timing” on page 300 for timing details. The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth.
When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. 24.5.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.
Thanks to these four values and the linear characteristics of the temperature sensor and Internal RC Oscillator, firmware can easily recalibrate the RC Oscillator on-the-go in function of the temperature sensor measure(3) (an application note describes the operation): Figure 24-8. Linear Characterization of OSCCAL in Function of T° Measurement from ADC OSCCAL O2 O1 T1 Notes: 1. 2. 3. 24.
The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Figure 24-10. ADC Power Connections VCC 34 GND 35 (ADC7) PF7 36 (ADC6) PF6 37 (ADC5) PF5 38 (ADC4) PF4 39 (ADC1) PF1 40 (ADC0) PF0 41 10µH AREF 42 GND AVCC 100nF 43 44 1 Analog Ground Plane Note: The same circuitry should be used for AVCC filtering on the ADC8-ADC13 side. 24.7.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible.
Figure 24-11. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 24-12.
Figure 24-13. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 24-14. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 24.
V IN 1023 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 24-3 on page 313 and Table 24-4 on page 313). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Figure 24-15. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 24-2. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 0.
̶ ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: ̶ ADMUX = 0xF0, MUX5 = 0 (ADC0 - ADC1, 1x gain, 2.56V reference, left adjusted result) ̶ Voltage on ADC0 is 300mV, voltage on ADC1 is 500mV ̶ ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 ̶ ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
24.9 ADC Register Description 24.9.1 ADC Multiplexer Selection Register – ADMUX Bit Read/Write Initial Value 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in the table. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 24-4. MUX5..0(1) Input Channel and Gain Selections Positive Differential Input Negative Differential Input Gain 001000 N/A N/A N/A 001001 ADC1 ADC0 10x 001010 N/A N/A N/A 001011 ADC1 ADC0 200x ADC1 1x 001100 Single Ended Input N/A 001101 N/A 001110 001111 010000 ADC0 010001 010010 N/A 010011 010100 ADC4 ADC1 1x 010101 ADC5 ADC1 1x 010110 ADC6 ADC1 1x ADC7 ADC1 1x ADC0 40x 010111 N/A 011000 011001 011010 011011 011100 011101 011110 1.
Table 24-4. MUX5..
• Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress.
24.9.3.2 ADLAR = 1 Bit Bit Read/Write Initial Value 15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 – 5 R R 0 0 12 ADC6 – 4 R R 0 0 11 ADC5 – 3 R R 0 0 10 ADC4 – 2 R R 0 0 9 ADC3 – 1 R R 0 0 8 ADC2 – 0 R R 0 0 ADCH ADCL When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read.
Table 24-6.
25. JTAG Interface and On-chip Debug System 25.0.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this fuse programmed.
Figure 25-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.3 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high.
The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio® supports source level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third party vendors’ compilers. AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT.
Refer to the debugger documentation for further information on how to use this register. 25.8 Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally.
26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features • • • • • 26.2 JTAG (IEEE std. 1149.
26.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 26.3.2 Device Identification Register Figure 26-1 shows the structure of the Device Identification Register. Figure 26-1.
Figure 26-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Internal reset Q ClockDR · AVR_RESET 26.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 329 for a complete description. 26.
26.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
• Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. 26.6 Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection. 26.6.
Boundary-scan Cell for bi-directional Port Pin with Pull-up Function To Next Cell ShiftDR EXTEST Pull-up Enable (PUE) Vcc 0 1 Output Control (OC) FF1 LD1 0 D Q D Q 0 1 1 G Output Data (OD) 0 1 FF0 LD0 0 D Q D 1 Q 0 1 Port Pin (PXn) Figure 26-3.
Figure 26-4.
26.7 Boundary-scan Order The table below shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pinout order as far as possible. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 26-3 on page 330, PXn.
Table 26-1. ATmega16U4/ATmega32U4 Boundary-scan Order Bit Number Signal Name 61 PD0.Data 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.
Table 26-1. ATmega16U4/ATmega32U4 Boundary-scan Order Bit Number Signal Name 41 Reserved 40 Reserved 39 Reserved 38 Reserved 37 Reserved 36 Reserved 35 Reserved 34 Reserved 33 Reserved 32 Reserved 31 Reserved 30 Reserved 29 Reserved 28 Reserved 27 Reserved 26 Reserved 25 PE2.Data 24 PE2.
Table 26-1. 26.8 ATmega16U4/ATmega32U4 Boundary-scan Order Bit Number Signal Name 23 Reserved 22 Reserved 21 Reserved 20 Reserved 19 Reserved 18 Reserved 17 Reserved 16 Reserved 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 Reserved 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 PF1.Data 2 PF1.Control 1 PF0.Data 0 PF0.
27. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
The limit between the RWW- and NRWW sections is given in Table 27-1 on page 337 and Figure 27-1 on page 338.
Figure 27-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW Section No Read-While-Write (NRWW) Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation Figure 27-2.
27.4 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.
27.5 Entering the Boot Loader Program The bootloader can be executed with three different conditions: 27.5.1 Regular Application Conditions A jump or call from the application program. This may be initiated by a trigger such as a command received via USART, SPI, or USB. 27.5.2 Boot Reset Fuse The Boot Reset Fuse (BOOTRST) can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.
Figure 27-3. Boot Process Description RESET tHHRH tSHRH ALE/HWB HWBE ? Ext. Hardware Conditions ? BOOTRST ? Reset Vector = Application Reset Reset Vector =Boot Lhoader Reset 27.5.4 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
on page 346 for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used. • Bit 4 – RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared).
27.6 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64KB.
27.7 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
27.7.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 63. 27.7.
three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set Manual.
Table 27-6. Signature Row Addressing Signature Byte Z-Pointer Address Device Signature Byte 1 0x0000 Device Signature Byte 2 0x0002 Device Signature Byte 3 0x0004 RC Oscillator Calibration Byte 0x0001 Note: All other addresses are reserved for future use. 27.7.11 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly.
; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
Read-While-Write Limit (Word Addresses)(1) Table 27-9. Device Section ATmega32U4 ATmega16U4 Note: 1. Table 27-10. Pages Address Read-While-Write section (RWW) 224 0x0000 - 0x37FF No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF Read-While-Write section (RWW) 97 0x0000 - 0x17FF No Read-While-Write section (NRWW) 32 0x1800 - 0x1FFF For details about these two section, see “NRWW – No Read-While-Write Section” on page 337 and “RWW – Read-While-Write Section” on page 337.
ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 351
ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 352
28. Memory Programming 28.1 Program And Data Memory Lock Bits The device provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. Lock Bit Byte() Table 28-1.
Lock Bit Protection Modes(1)(2) Table 28-2. Memory Lock Bits (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. 4 0 1 BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section.
Table 28-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
28.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 28.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
Parallel Programming(1) Figure 28-1. +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +5V AVCC PB7 - PB0 DATA RESET BS2 PE6 XTAL1 GND Note: 1. Unused Pins should be left floating. Table 28-6.
Table 28-7. BS2 and BS1 Encoding Flash Data Loading / Reading Fuse Programming Reading Fuse and Lock Bits BS2 BS1 Flash / EEPROM Address 0 0 Low Byte Low Byte Low Byte Fuse Low Byte 0 1 High Byte High Byte High Byte Lock bits 1 0 Extended High Byte Reserved Extended Byte Extended Fuse Byte 1 1 Reserved Reserved Reserved Fuse High Byte Table 28-8. Table 28-9.
Table 28-11. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega16U4 8K words (16KB) 64 words PC[5:0] 128 PC[12:6] 12 ATmega32U4 16K words (32KB) 64 words PC[5:0] 256 PC[13:6] 13 Table 28-12. No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 28.6.4 Programming the Flash The Flash is organized in pages, see Table 28-11 on page 359. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”.
3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (See Figure 28-3 on page 361 for signal waveforms). J. Repeat B through I until the entire Flash is programmed or until all data has been programmed K. End Page Programming 1. 1. Set XA1, XA0 to “10”.
Note: 1. “XX” is don’t care. The letters refer to the programming description above. 28.6.5 Programming the EEPROM The EEPROM is organized in pages, see Table 28-12 on page 359. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 360 for details on Command, Address and Data loading): 1.
28.6.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 360 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 28.6.
Figure 28-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 28.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 360 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
Figure 28-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte 0 Extended Fuse Byte 1 0 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 28.6.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 360 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS to “0”.
Figure 28-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. Figure 28-9. The timing requirements shown in Figure 28-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Table 28-13.
28.8 Serial Programming Pin Mapping Table 28-14. Pin Mapping Serial Programming Symbol Pins (TQFP-64) I/O Description PDI PB2 I Serial Data in PDO PB3 O Serial Data out SCK PB1 I Serial Clock Figure 28-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) PDI AVCC PDO SCK XTAL1 RESET GND Notes: 1. 2. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. VCC - 0.3V < AVCC < VCC + 0.
instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the seven LSB of the address and data together with the Load Program Memory Page instruction.
Table 28-16. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for Read Program Memory and Write Program Memory Page.
Table 28-16. Serial Programming Instruction Set Instruction Format Instruction Read Fuse High bits Byte 1 Byte 2 Byte 3 Byte4 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed, “1” = unprogrammed. 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. See Table 28-3 on page 354 for details.
Figure 28-12. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 28.9.2 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
Capture-DR: The result of the previous command is loaded into the Data Register Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command Update-DR: The programming command is applied to the Flash inputs Run-Test/Idle: One clock cycle is generated, executing the applied command 28.9.5 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
28.9.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 28-13.
Table 28-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 0100011_10000000 xxxxxxx_xxxxxxxx 0110001_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
Table 28-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b.
Table 28-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx 8a.
8. The bit mapping for Fuses Low byte is listed in Table 28-5 on page 355. 9. The bit mapping for Lock bits byte is listed in Table 28-1 on page 353. 10. Address bits exceeding PCMSB and EEAMSB (Table 28-11 on page 359 and Table 28-12 on page 359) are don’t care. 11. All TDI and TDO sequences are represented by binary digits (0b...). Figure 28-15.
new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 28-16.
28.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 28-13 on page 366). 28.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 380. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
3. Load the page address using programming instructions 3b, 3c, and 3d. PCWORD (refer to Table 28-11 on page 359) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash).
28.9.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 28-13 on page 366). 28.9.22 Reading the Fuses and Lock Bits 1.
29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature. . . . . . . . . . . . -40C to +85C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
Table 29-1. DC Characteristic, TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) Min.(5) Typ. Max.(5) Units 1 µA Symbol Parameter Condition IIH Input Leakage Current I/O Pin VCC = 5.
5. 6. 7. 8. 29.3 1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA. 2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA. 3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA. 4)The sum of all IOH, for ports F0-F7 should not exceed 100mA. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology.
29.5 System and Reset Characteristics Table 29-3. Reset and Brown-out Detection Characteristics Symbol VPOT Parameter Condition Min. Typ. Max. Units Power-on Reset Threshold Voltage (rising) 1.4 2.3 V Power-on Reset Threshold Voltage (falling)() 1.3 2.3 V +0.1 V VPOR VCC Start Voltage to ensure internal Power-on Reset signal -0.1 VCCRR VCC Rise Rate to ensure internal Power_on Reset signal 0.3 VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin V/ms 0.
Table 29-4. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) (1) VOL tr (1) Min. Max. Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.7VCC VCC + 0.5 0.05VCC(2) – 0 0.
4. fCK = CPU clock frequency. 5. This requirement applies to all ATmega16U4/ATmega32U4 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7.
Figure 29-4. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) Figure 29-5. MSB ... LSB SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 29.9 17 MSB ... LSB X Hardware Boot Entrance Timing Characteristics Figure 29-6.
Table 29-7. Symbol ADC Characteristics Parameter Resolution TUE INL DNL Absolute accuracy Integral Non-Linearity Differential Non-Linearity Gain Error Offset Error VREF Reference Voltage AVCC Analog Supply Voltage VIN Input Voltage Input Bandwidth Condition Min. Typ. Single Ended Conversion 10 Differential conversion, gain = 1x/10x/40x 8 Differential conversion, gain = 200x 8 Max. Bits VREF = 4V, VCC = 4V, ADC clock = 200kHz 2.0 3.
Table 29-7. ADC Characteristics Symbol Parameter Condition Min. Typ. Max. Units VINT Internal Voltage Reference 2.56V 2.4 2.56 2.
30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
Figure 30-2. Active Supply Current vs. Low Frequency (1MHz) and T= 85°C 2.3 5.5V I CC (mA) 2.1 1.9 5.0V 1.7 4.5V 1.5 4.0V 3.6V 1.3 2.7V 1.1 0.9 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Active Supply Current vs. Frequency (1 - 16MHz) and T= -40°C 18 ICC (mA) Figure 30-3. 16 5.5V 14 5.0V 12 4.5V 10 4.0V 8 3.6V 6 2.
Figure 30-4. Active Supply Current vs. Frequency (1 - 16MHz) and T = 25°C 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 4.0V 8 3.6V 6 4 2.7V 2 0 2 4 6 8 10 12 14 16 Frequency (MHz) Active Supply Current vs. Frequency (1 - 16MHz) and T = 85°C 16 5.5V 14 5.0V 12 4.5V 10 ICC (mA) Figure 30-5. 4.0V 8 3.6V 6 4 2.
Idle Supply Current Figure 30-6. Idle Supply Current vs. Low Frequency (1MHz) and T = 25°C I CC (mA) 0.5 0.45 5.5V 0.4 5.0V 0.35 4.5V 0.3 4.0V 3.6V 0.25 0.2 2.7V 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-7. Idle Supply Current vs. Low Frequency (1MHz) and T = 85°C 0.5 5.5V 0.45 I CC (mA) 30.2 0.4 5.0V 0.35 4.5V 0.3 4.0V 3.6V 0.25 2.7V 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 30-8. Idle Supply Current vs. Frequency (1 - 16MHz) T = 25°C 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 3.3V 2.7V 1 0 2 4 6 8 10 12 14 16 Frequency (MHz) Idle Supply Current vs. Frequency (1 - 16MHz) T = 85°C 7 5.5V 6 5.0V 5 ICC (mA) Figure 30-9. 4.5V 4 4.0V 3 3.6V 2 2.
Power-down Supply Current Figure 30-10. Power-Down Supply Current vs. VCC (WDT Disabled) 3.5 85°C 3 I CC (µA) 2.5 2 1.5 1 25°C -40°C 0.5 0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 V CC (V) Figure 30-11. Power-Down Supply Current vs. VCC (WDT Enabled) 24 85°C 22 20 18 16 I CC (µA) 30.3 25°C 14 12 -40°C 10 8 6 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 30-12. Power-down Supply Current vs. VCC (WDT Enabled, BOD EN) 48 85°C 45 42 I CC (µA) 39 25°C 36 -40°C 33 30 27 24 21 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 V CC (V) Power-save Supply Current Figure 30-13. Power-save Supply Current vs. VCC (WDT Disabled) 200 -40°C 25°C 85°C 185 170 155 140 I CC (µA) 30.4 125 110 95 80 65 50 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Pin Pull-Up Figure 30-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 I OP (µA) 50 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1 1.5 2 2.5 3 V OP (V) Figure 30-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 I OP (µA) 30.
Figure 30-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC= 5V) 120 100 I RESET (µA) 80 60 40 25°C 85°C -40°C 20 0 0 1 2 3 4 5 V RESET (V) Pin Driver Strength Figure 30-17. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 4 85°C 3.5 3 2.5 V OL (V) 30.6 2 1.5 25°C 1 -40°C 0.
Figure 30-18. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 1 85°C 0.9 0.8 25°C 0.7 V OL (V) 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 I OL (mA) Figure 30-19. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 V OH (V) 2.5 2 -40°C 1.5 25°C 1 0.
Figure 30-20. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 4.9 V OH (V) 4.7 4.5 -40°C 4.3 25°C 85°C 4.1 3.9 0 2 4 6 8 10 12 14 16 18 20 I OH (mA) Figure 30-21. USB DP LO Pull-Up Resistor Current vs. USB Pin Voltage 2800 2400 I USB (µA) 2000 1600 1200 800 85°C 400 25°C -40°C 0 0 0.5 1 1.5 2 2.5 3 3.
Pin Threshold and Hysteresis Figure 30-22. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 1.8 -40°C 25°C 85°C 1.6 Threshold (V) 1.4 1.2 1 0.8 0.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 V CC (V) Figure 30-23. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin read as ‘0’) 1.8 -40°C 25°C 85°C 1.6 1.4 Threshold (V) 30.7 1.2 1 0.8 0.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 30-24. USB Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 2 85°C 25°C 1.9 Threshold (V) 1.8 -40°C 1.7 1.6 1.5 1.4 1.3 1.2 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 V CC (V) Figure 30-25. USB Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 1.6 -40°C 85°C 25°C 1.5 Threshold (V) 1.4 1.3 1.2 1.1 1 0.9 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.
Figure 30-26. Vbus Pin Input Threshold Voltage vs. VCC (VIH, IO Pin read as ‘1’) 4.6 4.58 85°C 4.56 25°C Threshold (V) 4.54 4.52 4.5 4.48 4.46 4.44 4.42 4.4 -40°C 4.38 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 V CC (V) Figure 30-27. Vbus Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 1.52 85°C 25°C 1.51 Threshold (V) 1.5 1.49 1.48 1.47 -40°C 1.46 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
BOD Threshold Figure 30-28. BOD Thresholds vs. Temperature (BODLEVEL is 2.6V) 2.8 Rising Vcc 2.78 Threshold (V) 2.76 2.74 Falling Vcc 2.72 2.7 2.68 2.66 2.64 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-29. BOD Thresholds vs. Temperature (BODLEVEL is 3.5V) 3.73 Rising Vcc 3.69 Falling Vcc 3.65 Threshold (V) 30.8 3.61 3.57 3.53 3.49 3.
Figure 30-30. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.6 4.55 Falling Vcc Rising Vcc 4.5 Threshold (V) 4.45 4.4 4.35 4.3 4.25 4.2 4.15 4.1 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-31. Bandgap Voltage vs. VCC 1.11 Bandgap Voltage (V) 1.1 1.09 85°C 25°C 1.08 1.07 1.06 -40°C 1.05 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-32. Bandgap Voltage vs. Temperature 1.11 1.9V 3.0V 4.5V 5.0V 5.5V Bandgap Voltage (V) 1.1 1.09 1.08 1.07 1.06 1.05 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Internal Oscillator Speed Figure 30-33. Watchdog Oscillator Frequency vs. Temperature 124 122 120 F RC (kHz) 30.9 118 1.9V 116 3.0V 4.0V 4.5V 5.
Figure 30-34. Watchdog Oscillator Frequency vs. VCC 124 122 -40°C F RC (kHz) 120 25°C 118 116 114 85°C 112 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 30-35. Calibrated 8MHz RC Oscillator Frequency vs.
Figure 30-36. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.4 2.7V 4.0V 5.5V 8.3 F RC (MHz) 8.2 8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-37. Calibrated 8MHz RC Oscillator Frequency vs. Operating Voltage 8.4 8.3 85°C 8.2 F RC (MHz) 8.1 8 25°C 7.9 7.8 -40°C 7.7 7.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 30-38. OSCCAL VALUE STEP SIZE IN% (Base frequency = 0.0MHz) 1.4 1.2 F RC change (%) 1 0.8 0.6 0.4 85°C 0.2 -40°C 25°C 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 30.10 Current Consumption of Peripheral Units Figure 30-39. USB Regulator Level vs. VCC 3.5 3.4 -40°C 85°C 3.3 25°C I CC (µA) 3.2 3.1 3 2.9 2.8 2.7 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.
Figure 30-40. USB Regulator Level with load 75 vs. VCC 3.4 -40°C 85°C 25°C 3.3 3.2 Current (µA) 3.1 3 2.9 2.8 2.7 2.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 V CC (V) Figure 30-41. ADC Internal VREF vs. VCC 2.54 2.53 Voltage VIntRef (V) 2.52 2.51 85°C 25°C 2.5 2.49 2.48 2.47 2.46 -40°C 2.45 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5 5.3 5.
Figure 30-42. Internal Reference Voltage vs. Sink Current 2.52 85°C 25°C 2.51 Voltage VIntRef (V) 2.5 2.49 2.48 2.47 2.46 -40°C 2.45 2.44 2.43 -7 -6 -5 -4 -3 -2 -1 0 Sink current (mA) 30.11 Current Consumption in Reset and Reset Pulse Width Figure 30-43. Reset Supply Current vs. Frequency (1 - 20MHz) ICC (mA) 3.5 5.5V 3 5.0V 2.5 4.5V 2 4.0V 3.6V 1.5 1 2.7V 0.
31.
Address Name (0xBE) TCNT4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 (0xB8) TWBR (0xB7) Reserved - (0xB6) Reserved - (0xB5) Reserved (0xB4) Reserved (0xB3) Page Timer/Counter4 - Counter Register Low Byte 2-wire Se
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH (0x78) ADCL (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - - - - - (0x72) TIMSK4 OCIE4D OCIE4A OCIE4B - - TOIE4 - - (0x71) TIMSK3 - - ICIE3 - OCIE3C OCIE3B OCIE3A TOIE3 (0x70) Reser
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x17 (0x37) Reserved - - - - - - - - 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 - - PORTF1 PORTF0 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 - - DDF1 DDF0 0
32.
Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), R
Mnemonics Operands Description Operation Flags OUT P, Rr Out Port P Rr None #Clocks 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific description for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific description for WDR/timer) For On-chip Debug Only None None 1 N/A ATmega16U4/32U4 [DATASHEET SUMMARY] Atmel-7766J-USB-ATmega16U4/3
33. Ordering Information 33.1 ATmega16U4 Speed [MHz] 16 Power Supply 2.7 - 5.5V Ordering Code Default Oscillator ATmega16U4-AU External XTAL ATmega16U4RC-AU Internal Calib. RC ATmega16U4-MU ATmega16U4RC-MU Notes: 1. 2. 3. Operation Range 44ML Industrial (-40° to +85°C) External XTAL (1)(2)(3) (1)(2)(3) Package 44PW Internal Calib.
33.2 ATmega32U4 Speed [MHz] 16 Power Supply 2.7 - 5.5V Ordering Code Default Oscillator ATmega32U4-AU External XTAL ATmega32U4RC-AU Internal Calib. RC ATmega32U4-MU(1)(2)(3) External XTAL ATmega32U4RC-MU(1) (2) (3) Notes: 1. 2. 3. Package Internal Calib. RC Operation Range 44ML Industrial (-40° to +85°C) 44PW For more information on running the USB from internal RC oscillator consult application note AVR291: 8MHz Internal Oscillator Calibration for USB Low Speed on Atmel ATmega32U4RC.
34. Packaging Information 34.1 TQFP44 0.17 0.60 0.
34.
ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 425
35. Errata The revision letter in this section refers to the revision of the ATmega16U4/ATmega32U4 device. 35.1 ATmega16U4/ATmega32U4 Rev E • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • MSB of OCR4A/B/D is write only in 11-bits enhanced PWM mode 1. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/work around Enable ATmega16U4/ATmega32U4 TWI before the other nodes of the TWI network. 2.
35.3 ATmega16U4/ATmega32U4 Rev C Not sampled 35.4 ATmega16U4/ATmega32U4 Rev B • • • • Spike on TWI pins when TWI is enabled High current consumption in sleep mode Incorrect execution of VBUSTI interrupt Timer 4 11-bits enhanced PWM mode 1. Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem Fix/work around Enable ATmega16U4/ATmega32U4 TWI before the other nodes of the TWI network. 2.
If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/work around Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 3. Increased power consumption in power-down mode The typical power consumption is increased by about 30 µA in power-down mode. Problem Fix/work around None. 4.
36. Datasheet Revision History for ATmega16U4/ATmega32U4 Note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev. 7766J – 04/2016 1. 36.2 36.3 “Memory Programming” on page 353: Updated number of words in a page and number of pages in the Flash and EEPROM for ATmega16U4 and ATmega32U4. Refer to Table 28-11 and Table 28-12 on page 359. Rev. 7766I – 07/2015 1.
36.4 36.5 36.6 Rev. 7766G – 02/2014 1. Updated the “Description” on page 177 of the “Output Compare Modulator (OCM1C0A)” . Specified when the logical AND and the logical OR will be performed based on the PORTB7. 2. Updated “USART Control and Status Register n D– UCSRnD” on page 213. “Bits 7:2 Reserved” are Read only. 3. Updated “Crystal-less Operation” on page 259. The temperature range changed to “within the 0C and +40C. 4.
36.7 36.8 11. Added “Typical Characteristics” on page 392. 12. Updated “Ordering Information” on page 421. 13. Updated “Errata” on page 426. Rev. 7766D – 01/09 1. Updated Memory section in “Features” on page 1. 2. Added section “Resources” on page 8. 3. Added section “Data Retention” on page 8. 4. Updated “Ordering Information” on page 421. Rev. 7766C – 11/08 1. 36.9 Updated Memory section in “Features” on page 1. Rev. 7766B – 11/08 1. Added ATmega16U4 device. 2.
Table of Contents 1. Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 2.2 3. About . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.
7.9 8. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 9. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Resetting the AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . .
14.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.9 Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.10 16-bit Timer/Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 15. 10-bit High Speed Timer/Counter4 . . . . . . . . . . . . . . . . . . . . . . . .
20.4 20.5 20.6 20.7 20.8 20.9 Multi-master Bus Systems, Arbitration and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of the TWI Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6 24.7 24.8 24.9 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Noise Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .
29.6 29.7 29.8 29.9 Maximum speed vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-wire Serial Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-7766I-USB-ATmega16U4-32U4-Datasheet_07/2015. Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio®, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® is a registered trademark of Microsoft Corporation in U.S. and or other countries.
