Datasheet

14.2.2. Toggling the Pin
Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI
instruction can be used to toggle one single bit in a port.
14.2.3. Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11),
an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn,
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-
impedance environment will not notice the difference between a strong high driver and a pull-up. If this is
not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use
either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an
intermediate step.
The following table summarizes the control signals for the pin value.
Table 14-1. Port Pin Configurations
DDxn PORTxn PUD
(in MCUCR)
I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
14.2.4. Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn
Register bit. As shown in Ports as General Digital I/O, the PINxn Register bit and the preceding latch
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the
edge of the internal clock, but it also introduces a delay. The following figure shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 14-3. Synchronization when Reading an Externally Applied Pin value
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is
closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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