Datasheet

13.2.9. Pin Change Mask Register 0

Name: PCMSK0

Offset: 0x6A

Reset: 0x00

Property:

Bit 7 6 5 4 3 2 1 0

PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – PCINTn: Pin Change Enable Mask [n = 7:0]

Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If

PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding

I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016