Datasheet

13.2.8. Pin Change Mask Register 1

Name: PCMSK1

Offset: 0x6B

Reset: 0x00

Property:

Bit 7 6 5 4 3 2 1 0

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT8, PCINT9, PCINT10, PCINT11, PCINT12, PCINT13, PCINT14,

PCINT15: Pin Change Enable Mask

Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If

PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016