Datasheet

13.2.4. Pin Change Interrupt Control Register

Name: PCICR

Offset: 0x68

Reset: 0x00

Property:

Bit 7 6 5 4 3 2 1 0

PCIE3 PCIE2 PCIE1 PCIE0

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bit 3 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is

enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt. The corresponding

interrupt of Pin Change Interrupt Request is executed from the PCI3 Interrupt Vector. PCINT[31:24] pins

are enabled individually by the PCMSK3 Register.

Bit 2 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is

enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding

interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins

are enabled individually by the PCMSK2 Register.

Bit 1 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is

enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt

of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are

enabled individually by the PCMSK1 Register.

Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is

enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt

of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled

individually by the PCMSK0 Register.

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016