Datasheet

13.2.1. External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Name: EICRA

Offset: 0x69

Reset: 0x00

Property:

Bit 7 6 5 4 3 2 1 0

ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:6 – ISC3n: Interrupt Sense Control 3 [n = 1:0]

The External Interrupt 3 is activated by the external pin INT3 if the SREG I-flag and the corresponding

interrupt mask are set. The level and edges on the external INT3 pin that activate the interrupt are defined

in table below. The value on the INT3 pin is sampled before detecting edges. If edge or toggle interrupt is

selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not

guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the

completion of the currently executing instruction to generate an interrupt.

Value Description

00 The low level of INT3 generates an interrupt request.

01 Any logical change on INT3 generates an interrupt request.

10 The falling edge of INT3 generates an interrupt request.

11 The rising edge of INT3 generates an interrupt request.

Bits 5:4 – ISC2n: Interrupt Sense Control 2 [n = 1:0]

The External Interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding

interrupt mask are set. The level and edges on the external INT2 pin that activate the interrupt are defined

in table below. The value on the INT2 pin is sampled before detecting edges. If edge or toggle interrupt is

selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not

guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the

completion of the currently executing instruction to generate an interrupt.

Value Description

00 The low level of INT2 generates an interrupt request.

01 Any logical change on INT2 generates an interrupt request.

10 The falling edge of INT2 generates an interrupt request.

11 The rising edge of INT2 generates an interrupt request.

Bits 3:2 – ISC1n: Interrupt Sense Control 1 [n = 1:0]

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding

interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined

in the table below. The value on the INT1 pin is sampled before detecting edges. If edge or toggle

interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter

pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be

held until the completion of the currently executing instruction to generate an interrupt.

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016