Datasheet

10.8.1. Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SMCR
Offset: 0x53
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x33
Bit 7 6 5 4 3 2 1 0
SM2 SM1 SM0 SE
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – SM2: Sleep Mode Select 2
The SM[2:0] bits select between the five available sleep modes.
Table 10-2. Sleep Mode Select
SM2,SM1,SM0 Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Reserved
100 Reserved
101 Reserved
110 Standby
(1)
111 Reserved
Note:
1. Standby mode is only recommended for use with external .
Bit 2 – SM1: Sleep Mode Select 1
Refer to SM2.
Bit 1 – SM0: Sleep Mode Select 0
Refer to SM2.
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP
instruction and to clear it immediately after waking up.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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