Datasheet

ManualsBrandsMicrochip ManualsAVR MicrocontrollersAVR RISC Microcontroller Flash 32KB TQFP

10. PM - Power Management and Sleep Modes

10.1. Sleep Modes

The following Table shows the different sleep modes and their wake-up sources.

Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Sleep Mode Active Clock Domains Oscillators Wake-up Sources

clk

CPU

clk

FLASH

clk

ADC

clk

PLL

Main Clock Source Enabled INT3..0 PSC SPM/EEPROM

Ready

ADC WDT Other I/O

Idle Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

ADC Noise

Reduction

Yes Yes Yes Yes

(2)

Yes Yes Yes Yes

Power-down Yes

(2)

Yes

Standby

(1)

Yes Yes

(2)

Yes

1. Note: Only recommended with external crystal or resonator selected as clock source.

2. Note: Only level interrupt.

To enter any of the six sleep modes, the Sleep Enable bit in the Sleep Mode Control Register (SMCR.SE)

must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits

(SMCR.SM[2:0]) select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save,

Standby, or Extended Standby) will be activated by the SLEEP instruction.

Note: The block diagram in the section System Clock and Clock Options provides an overview over the

different clock systems in the device, and their distribution. This figure is helpful in selecting an

appropriate sleep mode.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then

halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes

execution from the instruction following SLEEP. The contents of the Register File and SRAM are

unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up

and executes from the Reset Vector.

10.2. Idle Mode

When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing the SPI, USART, Analog Comparator, 2-wire Serial Interface, Timer/

Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts

clk

CPU

and clk

FLASH

, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the

Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator

interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the

Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle

mode.