Datasheet

9.11.2. PLL Control and Status Register

Name: PLLCSR

Offset: 0x49

Reset: 0x0

Property:

R/W

Bit 7 6 5 4 3 2 1 0

PLLF PLLE PLOCK

Access

R/W R/W R

Reset 0 x 0

Bit 2 – PLLF: PLL Factor

The PLLF bit is used to select the division factor of the PLL.

Value Description

1 If PLLF is set, the PLL output is 64MHz.

0 If PLLF is cleared, the PLL output is 32MHz.

Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL

reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLKPLL for

Fast Peripherals. After the PLL is enabled, it takes about 100ms for the PLL to lock..

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016