Datasheet

Table 9-6. Start-Up Times for the Internal Calibrated RC Oscillator Clock Selection - SUT
Power Conditions Start-Up Time from Power-down
and Power-Save
Additional Delay from Reset (V
CC
=
5.0V)
SUT[1:0]
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4ms 01
Slowly rising power 6 CK 14CK + 65ms 10
(1)
Reserved 11
Note:
1. The device is shipped with this option selected.
Related Links
System Clock Prescaler on page 54
Calibration Byte on page 379
OSCCAL on page 56
9.6. PLL
9.6.1. Internal PLL
The internal PLL in Atmel ATmega16M1/32M1/64M1 generates a clock frequency that is 64× multiplied
from nominally 1MHz input. The source of the 1MHz PLL input clock is the output of the internal RC
Oscillator which is divided down to 1MHz.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust
the fast peripheral clock at the same time. However, even if the possibly divided RC Oscillator is taken to
a higher frequency than 1MHz, the fast peripheral clock frequency saturates at 70MHz (worst case) and
remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked
any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1MHz in
order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit
in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is set when PLL is locked.
Both internal 1MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep modes.
Table 9-7. Start-up times when the PLL is selected as system clock
CKSEL 3..0 SUT1..0 Start-up time from power-down
and power-save
Additional delay from reset
(VCC = 5.0V)
0011 RC Osc
00 1K CK 14CK
01 1K CK 14CK + 4ms
10 1K CK 14CK + 64ms
11 16K CK 14CK
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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