Datasheet

9. System Clock and Clock Options
9.1. Clock Systems and Their Distribution
The following figure illustrates the principal clock systems in the device and their distribution. All the
clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes. The clock systems are described in the
following sections.
The system clock frequency refers to the frequency generated from the System Clock Prescaler. All clock
outputs from the AVR Clock Control Unit runs in the same frequency.
Figure 9-1. Clock Distribution
Fast Peripherals ADC AVR CPU
Flash and
EEPROM
Watchdog
Timer
System Clock
Prescaler
Clock
Multiplexer
Watcdog
Oscillator
Calibrated Internal
RC OSC
External Clock
Crystal
Oscillator
clk
CPU
Reset Logic
AVR Clock
Control Unit
General I/O
Modules
RAM
clk
IO
clk
FLASH
clk
ADC
Watchdog clock
clk
SYS
PLL Clock
Multiplexer
PLL
clk
PLL
9.1.1. CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the General Purpose Register File, the Status Register and the data memory holding
the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and
calculations.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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