Datasheet

Note: In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
<12MHz
- 3 t
CLCL
for f
CK
>12MHz
Figure 29-3. SPI interface timing requirements (Master mode).
MOS I
(D
ata Output)
SCK
(CP OL = 1)
MISO
(D
ata Input)
SCK
(CP OL = 0)
SS
MSB LSB
L
SBMSB
...
...
6 1
2 2
34 5
8
7
Figure 29-4. SPI interface timing requirements (Slave mode).
MISO
(Data Output)
SCK
(CP OL = 1)
MO
SI
(Data Input)
SCK
(CP OL = 0)
SS
MSB LSB
L
SBMSB
...
...
10
11 11
121
3 14
17
15
9
X
16
Related Links
SPCR0 on page 220
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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