Datasheet

29.7. PLL characteristics
Table 29-6. PLL characteristics - V
CC
= 2.7V to 5.5V (unless otherwise noted).
Symbol Parameter Min. Typ. Max. Units
PLLIF Input frequency 0.5 1 2 MHz
PLLF PLL factor 64
PLLLT Lock-in time 64 µS
Note: While connected to external clock or external oscillator, PLL Input Frequency must be selected to
provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC...).
29.8. SPI timing characteristics
See the figures below for details.
Table 29-7. SPI timing parameters.
Description Mode Min. Typ. Max. Units
1 SCK period Master See the SPI Control
register
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 × tsck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 × tck
11 SCK high/low
(1)
Slave 2 × tck
12 Rise/Fall time Slave 1600
13 Setup Slave 10
14 Hold Slave tck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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