Datasheet

busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in
Watchdog Timer chapter, or the interrupts must be disabled. Before addressing the RWW section after
the programming is completed, the user software must clear the SPMCSR.RWWSB by writing the
SPMCSR.RWWSRE. Please refer to Simple Assembly Code Example for a Boot Loader for an example.
Related Links
Watchdog System Reset on page 69
27.8.7. Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write “0x0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1
The tables in Boot Loader Lock Bits show how the different settings of the Boot Loader bits affect the
Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction
is executed within four cycles after BLBSET and SPMEN are set in SPMCSR (SPMCSR.BLBSET and
SPMCSR.SPMEN). The Z-pointer don’t care during this operation, but for future compatibility it is
recommended to load the Z-pointer with 0x0001 (same as used for reading the lO
ck
bits). For future
compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When
programming the Lock bits the entire Flash can be read during the operation.
27.8.8. EEPROM Write Prevents Writing to SPMCSR
An EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
bits from software will also be prevented during the EEPROM write operation. It is recommended that the
user checks the status bit (EEPE) in the EECR Register (EECR.EEPE) and verifies that the bit is cleared
before writing to the SPMCSR Register.
27.8.9. Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits (LB) from software. To read the Lock bits, load the Z-
pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR (SPMCSR.BLBSET and
SPMCSR.SPMEN). When an LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN), the value of the Lock bits
will be loaded in the destination register. The SPMCSR.BLBSET and SPMCSR.SPMEN will auto-clear
upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When SPMCSR.BLBSET and SPMCSR.SPMEN
are cleared, LPM will work as described in the Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1
The algorithm for reading the Fuse Low byte (FLB) is similar to the one described above for reading the
Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN
bits in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN). When an LPM instruction is executed within
three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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