Datasheet

can be accessed in a random sequence. It is essential that the page address used in both the Page

Erase and Page Write operation is addressing the same page. Please refer to Simple Assembly Code

Example for a Boot Loader.

27.8.1. Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “0x0000011” to Store Program Memory

Control and Status Register (SPMCSR) and execute SPM within four clock cycles after writing SPMCSR.

The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other

bits in the Z-pointer will be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

27.8.2. Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in [R1:R0], write “0x00000001”

to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD

([Z5:Z1]) in the Z-register is used to address the data in the temporary buffer. The temporary buffer will

auto-erase after a Page Write operation or by writing the RWWSRE bit in SPMCSR

(SPMCSR.RWWSRE). It is also erased after a system reset. It is not possible to write more than one time

to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.

27.8.3. Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “0x0000101” to SPMCSR and execute

SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address

must be written to PCPAGE ([Z5:Z1]). Other bits in the Z-pointer must be written to zero during this

operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write

• Page Write to the NRWW section: The CPU is halted during the operation

27.8.4. Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit

in SPMCSR is cleared (SPMCSR.SPMEN). This means that the interrupt can be used instead of polling

the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved

to the Boot Loader Section (BLS) section to avoid that an interrupt is accessing the RWW section when it

is blocked for reading. How to move the interrupts is described in Interrupts chapter.