Datasheet

22.11.3. ADC Control and Status Register B
Name: ADCSRB
Offset: 0x7B
Reset: 0x00
Property: R/W
Bit 7 6 5 4 3 2 1 0
ADHSM ISRCEN AREFEN ADTS[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with an ADC
clock frequency higher than 200kHz.
Bit 6 – ISRCEN: Current Source Enable
Set this bit to source a 100μA current to the AREF pin. Clear this bit to use AREF pin as Analog
Reference pin.
Bit 5 – AREFEN: Analog Reference pin Enable
Set this bit to connect the internal AREF circuit to the AREF pin. Clear this bit to disconnect the internal
AREF circuit from the AREF pin.
Bits 3:0 – ADTS[3:0]: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE bit in
ADCSRA register is set.
These three bits select the interrupt event which will generate the trigger of the start of conversion. The
start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt
is enabled or not. In case of trig on PSCnASY event, there is no flag. So in this case a conversion will
start each time the trig event appears and the previous conversion is completed.
Value Description
0000 Free Running mode
0001 External interrupt request 0
0010 Timer/Counter0 compare match
0011 Timer/Counter0 overflow
0100 Timer/Counter1 compare Match B
0101 Timer/Counter1 overflow
0110 Timer/Counter1 capture event
0111 PSC Module 0 synchronization signal
1000 PSC Module 1 synchronization signal
1001 PSC Module 2 synchronization signal
1010 Analog comparator 0
1011 Analog comparator 1
1100 Analog comparator 2
1101 Analog comparator 3
1110 Reserved
1111 Reserved
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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