Datasheet

Figure 22-16. Amplifier synchronization timing diagram. ADSC is set when the amplifier output is changing
due to the amplifier clock switch.
Va lid s a mple
Signa l to be
me
asure d
AMP LI_clk
(
S ync clock)
CK ADC
ADSC
ADC
a borte d
PSC
block
Amplifie r
block
P
SC n_AS Y
Amplifie r
sample
enable
Amplifie r hold
v
alue
ADC
activity
ADC
conv
ADC
conv
ADC
sampling
ADC
sampling
ADC re
sult
re
ady
ADC re
sult
ready
ADC
sampling
In order to have a better understanding of the functioning of the amplifier synchronization, a timing
diagram example is shown in the figure above.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is
started at the next amplifier clock event following the last auto trigger event selected thanks to the ADTS
bits in the ADCSRB register. In auto trigger conversion, the free running mode is not possible unless the
ADSC bit in ADCSRA is set by soft after each conversion.
The block diagram of the two amplifiers is shown below.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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