Datasheet

Figure 22-15. Amplifier synchronization timing diagram. With change on analog input signal.
Va lid s a mple
De lta V
4th s ta ble s a mple
Signal to be
me
asured
AMP LI_clk
(
S ync clock)
CK ADC
PSC n_AS Y
PSC
block
ADSC
ADC
Amplifie r
block
Amplifie r
sample
en
able
Amplifie r hold
v
alue
ADC
activity
ADC
conv
ADC
conv
ADC
sampling
ADC
sampling
ADC re s ult
re
ady
ADC re
sult
re
ady
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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