Datasheet

Where:
• ADCH and ADCL are the ADC data registers.
• TSGAIN is the temperature sensor gain (constant 1, or unsigned fixed point number, 0x80 =
decimal 1.0).
• TSOFFSET is the temperature sensor offset correction term (2. complement signed byte).
22.10. Amplifier
The Atmel ATmega16M1/32M1/64M1 features three differential amplified channels with programmable 5,
10, 20, and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a synchronization
signal called in this document the amplifier synchronization clock. To ensure an accurate result, the
amplifier input needs to have a quite stable input value during at least four Amplifier synchronization clock
periods.
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the sampling
point during at least four amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events or to the internal clock CK
ADC
equal to eighth
the ADC clock frequency. In case the synchronization is done the ADC clock divided by 8, this
synchronization is done automatically by the ADC interface in such a way that the sample-and-hold
occurs at a specific phase of CK
ADC2
. A conversion initiated by the user (that is, all single conversions,
and the first free running conversion) when CK
ADC2
is low will take the same amount of time as a single
ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by
the user when CK
ADC2
is high will take 14 ADC clock cycles due to the synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits in the
AMPxCSR register. Then the amplifier can be switched on, and the amplification is done on each
synchronization event.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX must be
configured as specified on .
The ADC starting requirement is done by setting the ADSC bit of the ADCSRA Register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, two timing
diagram examples are shown below.
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started.
In case the amplifier output is modified during the sample phase of the ADC, the on-going conversion is
aborted and restarted as soon as the output of the amplifier is stable. This ensure a fast response time.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than ADCclk/4.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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