Datasheet

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any
CPU frequency above 100kHz. The prescaling is selected by the ADC Prescaler Select bits in the ADC
Control and Status Register A (ADCSRA.ADPS). The prescaler starts counting from the moment the ADC
is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as
long as ADEN=1, and is continuously reset when ADEN=0.
When initiating a single ended conversion by writing a '1' to the ADC Start Conversion bit
(ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (i.e.,
ADCSRA.ADEN is written to '1') takes 25 ADC clock cycles in order to initialize the analog circuitry.
When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage
to stabilize. If not stabilized, the first value read after the first conversion may be wrong.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conversion and
13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is
written to the ADC Data Registers (ADCL and ADCH), and the ADC Interrupt Flag (ADCSRA.ADIF) is set.
In Single Conversion mode, ADCSRA.ADSC is cleared simultaneously. The software may then set
ADCSRA.ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed
delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two
ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are
used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADCRSA.ADSC remains high. See also the ADC Conversion Time table below.
Figure 22-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample and Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 2
12
13
14 15
16 17
18 19 20 21 22
23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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