Datasheet

cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag
must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 22-2. ADC Auto Trigger Logic
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the
ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling
and updating the ADC Data Register. The first conversion must be started by writing a '1' to
ADCSRA.ADSC. In this mode the ADC will perform successive conversions independently of whether the
ADC Interrupt Flag (ADIF) is cleared or not.The free running mode is not allowed on the amplified
channels.
If Auto Triggering is enabled, single conversions can be started by writing ADCSRA.ADSC to '1'. ADSC
can also be used to determine if a conversion is in progress. The ADSC bit will be read as '1' during a
conversion, independently of how the conversion was started.
22.5. Prescaling and Conversion Timing
Figure 22-3. ADC Prescaler
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2 CK/4 CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and
2MHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to
the ADC can be higher than 2MHz to get a higher sample rate.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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