Datasheet

21.6.2. LIN Status and Interrupt Register
Name: LINSIR
Offset: 0xC9
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
LIDST[2:0] LBUSY LERR LIDOK LTXOK LRXOK
Access
Reset 0 0 0 0 0 0 0 0
Bits 7:5 – LIDST[2:0]: LIN Identifier Status
Value Description
0xx No specific identifier
100 Identifier 60 (0x3C)
101 Identifier 61 (0x3D)
110 Identifier 62 (0x3E)
111 Identifier 63 (0x3F)
Bit 4 – LBUSY: Busy Signal
Value Description
0 Not busy
1 Busy (receiving or transmitting)
Bit 3 – LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit -
LENERR - is set in LINENIR.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR
bits. In UART mode, this bit is also cleared by reading LINDAT.
Value Description
0 No error
1 An error has occurred
Bit 2 – LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
Value Description
0 No identifier
1 Slave task: Identifier present, master task: Tx Header complete
Bit 1 – LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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