Datasheet

– Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR
5. LINBTR
– LBT[5..0] are R/W access only if LDISR is set
– If LDISR is reset, LBT[5..0] are unchangeable
6. LINBRRH & LINBRRL
– All bits are R/W accessible
7. LINDLR
– All bits are R/W accessible
8. LINIDR
– LID[5..0] are R/W accessible
– LP[1..0] are Read accessible and are always updated on the fly
9. LINSEL
– All bits are R/W accessible
10. LINDAT
– All bits are R/W accessible
– Note that LAINC has no more effect on the auto-incrementation and the access to the full
FIFO is done setting LINDX[2..0] of LINSEL
– Note: When a debugger break occurs, the state machine of the LIN/UART controller is
stopped (included frame time-out) and further communication may be corrupted.
21.6. Register Description
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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