Datasheet

Table 21-4. Frame status
LIDST[2..0] Frame status
0xx
b
No specific identifier
100
b
60 (0x3C) identifier
101
b
61 (0x3D) identifier
110
b
62 (0x3E) identifier
111
b
63 (0x3F) identifier
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic
checksum (sum over the data bytes only). Software will be responsible for switching correctly the LIN13
bit to provide/check this expected checksum (the insertion of the ID field in the computation of the CRC is
set - or not - just after entering the Rx or Tx Response command).
21.5.15. Data management
21.5.15.1. LIN FIFO data buffer
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer accessible).
This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the LINDAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can be read or
written. The data index is automatically incremented after each LINDAT access if the LAINC (active low)
bit is cleared. A roll-over is implemented, after data index=7 it is data index=0. Otherwise, if LAINC bit is
set, the data index needs to be written (updated) before each LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1, and so on.
Nevertheless, LINSEL must be initialized by the user before use.
21.5.15.2. UART data register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data
out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
21.5.16. OCD support
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (that is I/O view
behavior in Atmel Studio
®
).
1. LINCR
– LINCR[6..0] are R/W accessible
– LSWRES always is a self-reset bit (needs one micro-controller cycle to execute)
2. LINSIR
– LIDST[2..0] and LBUSY are always Read accessible
– LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly by
writing 1 or 0)
– Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR bits
3. LINENR
– All bits are R/W accessible
4. LINERR
– All bits are R/W accessible
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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