Datasheet

21.5.5.1. Busy signal in LIN mode
Figure 21-7. Busy signal in LIN mode
BREAK
Field
SYNC
Field
CHECKSUM
Field
DATA-0
FieldField
IDENTIFIER
PROTECTED
DATA-n
Field
RESPONSEHEADER
FRAME SLOT
LIN bus
LIDOK
Node providing the master task
Node providing a slave task
LCMD=Tx header LTXOK or LRXOKLCMD=Tx or Rx response
1) LBUSY
3) LBUSY
2) LBUSY
Node providing neither the master task, neither a slave task
When the busy signal is set, some registers are locked, user writing is not allowed:
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES
• “LIN Baud Rate Registers” - LINBRRL & LINBRRH
• “LIN Data Length Register” - LINDLR
• “LIN Identifier Register” - LINIDR
• “LIN Data Register” - LINDAT
If the busy signal is set, the only available commands are:
• LCMD[1..0] = 00
b
, the abort command is taken into account at the end of the byte
• LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately
• LSWRES = 1, the reset command is taken into account immediately
Note that, if another command is entered during busy signal, the new command is not validated and the
LOVRERR bit flag of the LINERR register is set. The on-going transfer is not interrupted.
21.5.5.2. Busy signal in UART mode
During the byte transmission, the busy signal is set. This locks some registers from being written:
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES
• “LIN Data Register” - LINDAT
The busy signal is not generated during a byte reception.
21.5.6. Bit timing
21.5.6.1. Baud rate generator
The baud rate is defined to be the transfer rate in bits per second (bps):
• BAUD: Baud rate (in bps)
• clk
i/o
: System I/O clock frequency
• LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives clk
i/o
as
input clock
• LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a LIN or
UART bit (default value 32)
Equation for calculating baud rate:
BAUD = fclk
i/o
/ LBT[5..0] x (LDIV[11..0] + 1)
Equation for setting LINDIV value:
LDIV[11..0] = ( fclk
i/o
/ LBT[5..0] x BAUD ) - 1
Note that in reception a majority vote on three samplings is made.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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