Datasheet

The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic
checksum in LIN 1.3). See Rx & TX response functions.
This bit is irrelevant for UART commands.
21.5.4. Configuration
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the
following configuration:
Table 21-3. Configuration table versus mode.
Mode LCONF[1..0] Configuration
LIN 00
b
LIN standard configuration (default)
01
b
No CRC field detection or transmission
10
b
Frame_Time_Out disable
11
b
Listening mode
UART 00
b
8-bit data, no parity & 1 stop-bit
01
b
8-bit data, even parity & 1 stop-bit
10
b
8-bit data, odd parity & 1 stop-bit
11
b
Listening mode, 8-bit data, no parity & 1 stop-bit
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN
output pin is disabled and the RXLIN input pin is always enabled. The same scheme is available in UART
mode.
Figure 21-6. Listening mode.
1
0
TXLIN
RXLIN
internal
Tx LIN
internal
Rx LIN
LISTEN
21.5.5. Busy signal
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hardware. It
signals that the controller is busy with LIN or UART communication.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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