Datasheet

In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure the
LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response.
When the command starts, the controller checks the LIN13 bit of the LINCR register to apply the right rule
for computing the checksum. Checksum calculation over the DATA bytes and the PROTECTED
IDENTIFIER byte is called enhanced checksum and it is used for communication with LIN 2.1 slaves.
Checksum calculation over the DATA bytes only is called classic checksum and it is used for
communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C) to 63 (0x3F) shall always use classic
checksum.
At the end of this reception or transmission, the controller automatically returns to Rx Header / LIN Abort
state (that is LCMD[1..0] = 00) after setting the appropriate flags.
If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are set and the
LIN bus is left to recessive state.
During these functions, the controller is responsible for:
• The initialization of the checksum operator
• The transmission or the reception of ‘n’ data with the update of the checksum calculation
• The transmission or the checking of the CHECKSUM field
• The checking of the Frame_Time_Out
• The checking of the LIN communication integrity
While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and
the identifier of this new header will be recorded. Of course, specific errors on the previous response will
be maintained with this identifier reception.
21.4.6.4. Handling data of LIN response
A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL
register, repeated accesses to the LINDAT register perform data read or data write (see Data
management).
Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access.
21.4.7. UART commands
Setting the LCMD[2] bit in LINENR register enables UART commands. Tx Byte and Rx Byte services are
independent as shown in Table 21-1.
• Byte Transfer: the UART is selected but both Rx and Tx services are disabled
• Rx Byte: only the Rx service is enable but Tx service is disabled
• Tx Byte: only the Tx service is enable but Rx service is disabled
• Full Duplex: the UART is selected and both Rx and Tx services are enabled
This combination of services is controlled by the LCMD[1..0] bits of LINENR register (see Figure 21-5).
21.4.7.1. Data handling
The FIFO used for LIN communication is disabled during UART accesses. LRXDL[3..0] and LTXDL[3..0]
values of LINDLR register are then irrelevant. LINDAT register is then used as data register and LINSEL
register is not relevant.
21.4.7.2. Rx service
Once this service is enabled, the user is warned of an in-coming character by the LRXOK flag of LINSIR
register. Reading LINDAT register automatically clears the flag and makes free the second stage of the
buffer. If the user considers that the in-coming character is irrelevant without reading it, he directly can
clear the flag (see specific flag management described in Section 20.6.2 on page 208).
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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